News Column

Researchers Submit Patent Application, "Method and Apparatus for Leakage Suppression in Flash Memory in Response to External Commands", for Approval

August 28, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Kuo, Nai-Ping (Hsinchu City, TW); Lo, Su-Chueh (Hsinchu City, TW); Chang, Kuen-Long (Taipei, TW); Hung, Chun-Hsiung (Hsinchu, TW); Cheng, Chia-Feng (Changhua City, TW); Chen, Ken-Hui (Hsinchu City, TW); Wang, Yu-Chen (Kaohsiung City, TW), filed on April 9, 2014, was made available online on August 14, 2014.

The patent's assignee is Macronix International Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to flash memory technology, and more particularly to techniques for suppressing leakage in block-based flash memory devices.

"Flash memory includes memory cells that store charge between the channel and gate of a field effect transistor. The charge stored affects the threshold voltage of the transistor. Changes in the threshold voltage due to the stored charge can be sensed to indicate data stored in the memory cell. One type of charge storage cell is known as a floating gate memory cell, which stores charge on an electrically conductive layer between the channel and gate. Another type of charge storage cell is referred to as a charge trapping memory cell, which uses a dielectric layer in place of the floating gate.

"A memory cell can be programmed using various biasing techniques such as Fowler Nordheim (FN) tunneling, Channel Hot Electron (CHE), etc. The programming operation increases the threshold voltage of the memory cell.

"A memory cell can be erased by applying a bias to induce hole tunneling into the charge storage layer, or to induce electron tunneling from the charge storage layer. The erase operation decreases the threshold voltage of the memory cell.

"In a flash memory device, memory cells in an array are grouped into blocks, and memory cells in each block are erased together. Thus, in order to erase a memory cell in a block, all the memory cells in that block must also be erased. Consequently, an erase operation in a flash device is generally a slower process than a program operation.

"Flash memory devices can suffer from the problem of over-erasure of the memory cells. When a block of memory cells is erased, some of the memory cells will have a lower threshold voltage than others. Over-erasure occurs if, during the erasing step, too many electrons are removed from the charge storage layer. This can leave a slight positive charge, which biases the memory cell slightly on, such that the memory cell is operating in depletion mode. This results in the memory cell conducting leakage current, even when it is not accessed. A number of over-erased cells along a given bit line can cause an accumulation of leakage current sufficient to cause a false reading of a selected memory cell sharing the same bit line.

"For example, in a NOR architecture, drains of a number of memory cells are coupled together to a common bit line. If one or more memory cells has been over-erased, those memory cells will cause leakage current to flow on the common bit line, even when the cell is not directly accessed. During a read operation of a selected memory cell, the leakage current flowing on the common bit line due to the over-erased cell(s) can cause the current on the bit line to be high enough that the selected memory cell falsely appears to be erased.

"It is therefore desirable to provide flash memory devices and methods for operating which address the issues caused by over-erased cells."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Techniques are described herein for suppressing leakage current in a block-based flash memory device by detecting and recovering over-erased memory cells. An over-erased memory cell is a memory cell having a threshold voltage less than a minimum threshold voltage of an erased state.

"A leakage-suppression process is carried out by control logic in response to a command received on an external control line via a command interface. The command may be provided by a host computer or other external source. The leakage-suppression process may be a stand-alone process, or embedded within other operations. For example, the leakage-suppression process may be performed during standard block erase operations.

"The leakage-suppression process can include applying bias voltages sufficient to turn on over-erased memory cells, in order to identify corresponding bit lines that conduct leakage current. A significant leakage current indicates that the identified bit lines are coupled to one or more over-erased memory cells. A 'soft' program operation is then performed to slightly increase the threshold voltage of the over-erased memory cells, thereby correcting the over erasure.

"To support this process, erase status data associated with each block of memory cells can be maintained and stored in memory on the device. The erase status data is written to memory following successful completion of the leakage-suppression process on the corresponding block of memory cells. The erase status data can thus be used to quickly determine whether a corresponding block of memory cells may include over-erased memory cells.

"In some embodiments, the erase status data is a single bit flag indicating the over-erase status of the corresponding block. The flag is set, for example, prior to beginning the leakage-suppression process on the corresponding block. Upon successful completion of the leakage-suppression process, the flag is then reset to indicate that the block does not contain over-erased memory cells. Thus, the flag indicates whether an interruption, such as power down of the device, occurred prior to completion of the leakage-suppression process. If the flag is set, the control logic executes the leakage suppression process on the corresponding block of memory cells. If the flag is reset, the control logic skips the block without performing the leakage-suppression process.

"In other embodiments, the erase status data is a predetermined multi-bit sequence stored within a status field area of the corresponding block of memory cells. The predetermined multi-bit sequence is a pattern of programmed and erased bits written to memory cells in the status field area within the block. The predetermined bit sequence is written to the status field of the block upon erasing the memory cells in the block, but prior to performing the leakage-suppression process.

"A difference between the data stored in the status field area and the expected predetermined multi-bit sequence can be used to indicate that the corresponding block may include over-erased memory cells. As a result of the relatively small number of memory cells in the status field area, this determination can be made much more quickly than detecting bit errors within the entire block of memory cells.

"Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description, and the claims which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a simplified block diagram of a flash memory device including a memory array having bocks of memory cells which can be operated as described herein.

"FIG. 2 illustrates an example of a portion of a block of memory cells in the memory array of FIG. 1.

"FIG. 3 is a flow diagram of a leakage-suppression process for detecting and recovering over-erased memory cells.

"FIG. 4 is a flow diagram of a first example of the leakage-suppression process of FIG. 3

"FIG. 5 is a flow diagram of a second example of the leakage-suppression process of FIG. 3.

"FIG. 6 is a flow diagram for performing a leakage-suppression process that includes the setting and resetting of a single bit flag.

"FIG. 7 is a flow diagram of an operation for determining whether to perform the leakage-suppression process.

"FIG. 8 is a flow diagram of an erase operation that includes writing a predetermined bit-sequence upon erasing the memory cells in the block.

"FIG. 9 illustrates an example arrangement of data within blocks of memory cells which include a status field area.

"FIG. 10 illustrates a flow diagram of an operation for determining whether an interruption occurred during the erase operation of FIG. 8.

"FIG. 11 illustrates an example in which two bits within the status field area of a given block are read as being in the programmed state, while the expected bit sequence specifies that these bits should be in the erased state.

"FIG. 12 illustrates an example in which two bits within the status field area of a given block are read as being in the erased state, while the expected bit sequence specifies that these memory cells should be in the programmed state.

"FIG. 13 illustrates an example in which four bits within the status field area are read as being in the erased state, while the expected bit sequence specifies that these memory cells should be in the programmed state."

For additional information on this patent application, see: Kuo, Nai-Ping; Lo, Su-Chueh; Chang, Kuen-Long; Hung, Chun-Hsiung; Cheng, Chia-Feng; Chen, Ken-Hui; Wang, Yu-Chen. Method and Apparatus for Leakage Suppression in Flash Memory in Response to External Commands. Filed April 9, 2014 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4600&p=92&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Macronix International Co. Ltd.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Politics & Government Week


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters