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Patent Application Titled "Solid State Drive and Data Erasing Method Thereof" Published Online

August 28, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventor Hsieh, Shih-Hung (Hsinchu, TW), filed on June 18, 2013, was made available online on August 14, 2014.

No assignee for this patent application has been made.

Reporters obtained the following quote from the background information supplied by the inventors: "As is well known, a solid state drive (SSD) is a data storage device that uses a non-volatile memory to store data. After data are written to the non-volatile memory, if the system is powered off, the data are still retained in the solid state drive. For example, the non-volatile memory is a flash memory.

"Generally, the floating gate transistor of each cell of the flash memory has a floating gate to store hot carriers. Moreover, a storing state of the floating gate transistor is determined according to the amount of the stored hot carriers.

"Depending on the bit amount of data to be stored in each cell, the flash memories may be classified into a single-level cell (SLC) flash memory and a multi-level cell (MLC) flash memory. The SLC flash memory can store only one bit of data per cell and distinguish two storing states from each other. The MLC flash memory can store at least two bits of data per cell and distinguish at least four storing states from each other. For example, if the MLC flash memory can store two bits of data per cell, the MLC flash memory can distinguish four storing states from each other.

"FIG. 1 schematically illustrates the threshold voltage distribution curves of the MLC flash memory in different storing states. For example, the MLC flash memory can store two bits of data per cell. Before the cell is programmed, no hot carriers are injected into the cell. Consequently, the cell has the lowest threshold voltage (e.g. 0V). Under this circumstance, the cell may be considered to have a storing state '11' for example.

"During the program cycle, if a first program voltage Vp1 is provided to the cell, a small number of hot carriers are injected into the cell. Consequently, the threshold voltage of the cell is increased to about 10V, and the cell may be considered to have a storing state '10'. During the program cycle, if a second program voltage Vp2 is provided to the cell, more hot carriers are injected into the cell. Consequently, the threshold voltage of the cell is increased to about 20V, and the cell may be considered to have a storing state '01'. During the program cycle, if a third program voltage Vp3 is provided to the cell, the largest number of hot carriers are injected into the cell. Consequently, the threshold voltage of the cell is increased to about 30V, and the cell may be considered to have a storing state '00'. That is, the magnitude of the third program voltage Vp3>the magnitude of the second program voltage Vp2>the magnitude of the first program voltage Vp1.

"From the above discussions, the threshold voltage of the floating gate transistor is changed after the cell is programmed. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.

"That is, during the program cycle of the solid state drive, the amount of hot carriers to be injected into the floating gate are controlled according to the magnitude of the program voltage, and thus the threshold voltage of the floating gate transistor is changed to result in different storing states. Moreover, during a read cycle, a sensing circuit of the solid state drive may determine the storing state of the floating gate transistor according to the threshold voltage of the floating gate transistor.

"Generally, before the solid state drive is used, no data have been programmed into the flash memory. Under this circumstance, the cell of the flash memory has the storing state corresponding to the lowest threshold voltage. For example, as shown in FIG. 1, the cell of the flash memory has the storing state '11' before the flash memory is used.

"FIG. 2 is a flowchart illustrating a method of using a conventional solid state drive. After the solid state drive is used, the data are programmed into the flash memory (Step S202).

"After the data are programmed, the data may be read from the flash memory by a host (Step S204). Generally, the times of reading the data from the flash memory are not restricted.

"When the data in the flash memory are no longer used, the data of the flash memory are erased during an erase cycle (Step S206). Moreover, during the erase cycle of the solid state drive, an erase voltage is provided to erase the data.

"After the operations of the erase cycle of the solid state drive are completed, the cell of the flash memory is changed to an erase state. Consequently, the data may be programmed again (Step S202). Generally, the erase state of the cell is the storing state with the lowest threshold voltage. For example, if the flash memory can store two bits of data per cell, after the cell is erased, the cell is restored to the storing state '11'.

"Moreover, it is found that the use life of the solid state drive is related to the erase count. Ideally, after the erase cycle of the solid state drive is completed, the cell should be restored to the storing state '11', and no hot carriers are retained in the floating gate transistor. However, in practice, some of the hot carriers are possibly retained in the floating gate transistor and fail to be completely removed. Moreover, after many times of subsequent program cycles and erase cycles, the hot carriers are continuously accumulated in the floating gate and the gate oxide layer. Consequently, the use life of the solid state drive is shortened."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventor's summary information for this patent application: "The present invention provides a data erasing method of a solid state drive for effectively reducing the number of hot carriers that are retained in the floating gate and the gate oxide layer. Consequently, the hot carriers are not continuously accumulated, and the use life of the solid state drive is extended.

"An embodiment of the present invention provides a data erasing method of a solid state drive. The solid state drive includes a memory module. The memory module includes a block. A data to be erased is stored in the block. The data erasing method includes steps of performing a first erasing operation to erase the block, programming the block after the first erasing operation, and performing a second erasing operation to erase the block.

"Another embodiment of the present invention provides a solid state drive. The solid state drive includes a memory module and a controlling unit. The memory module includes a block, wherein a data to be erased is stored in the block. The controlling unit is used for providing a program voltage to the memory module during a program cycle. Moreover, the controlling unit is used for sequentially performing a first erasing operation to erase the block, programming the block and performing a second erasing operation to erase the block during an erase cycle.

"Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

"FIG. 1 (prior art) schematically illustrates the threshold voltage distribution curves of the MLC flash memory in different storing states;

"FIG. 2 (prior art) is a flowchart illustrating a method of using a conventional solid state drive;

"FIG. 3 is a schematic functional diagram illustrating a solid state drive according to an embodiment of the present invention; and

"FIG. 4 is a flowchart illustrating a method of using a solid state drive according to an embodiment of the present invention."

For more information, see this patent application: Hsieh, Shih-Hung. Solid State Drive and Data Erasing Method Thereof. Filed June 18, 2013 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4607&p=93&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Patents.

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Source: Politics & Government Week


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