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Patent Application Titled "Asymmetric Topology to Boost Low Load Efficiency in Multi-Phase Switch-Mode Power Conversion" Published Online

August 28, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Hardman, Peter Thomas (Kyle, TX); Pang, Erwin (Markham, CA); Lakhanpal, Sanjiv K. (Austin, TX), filed on April 10, 2014, was made available online on August 14, 2014.

The assignee for this patent application is Advanced Micro Devices, Inc.

Reporters obtained the following quote from the background information supplied by the inventors: "This application relates to power converter circuits and more particularly to DC to DC power converter circuits.

"DC to DC power converter circuits, which are particularly useful in low-power electronic devices, convert a source of direct current from a first voltage level to a second voltage level (FIG. 1). A typical switch-mode (Le., switched, switched-mode, switch-mode, switching-mode, etc.) DC to DC power converter converts the first voltage level to the second voltage level by temporarily storing energy in a magnetic component (e.g., an inductor or transformer) or a capacitor circuit (e.g., switched capacitor circuit) and then releasing the energy, at a different voltage, from the magnetic component to a load. In general, actual switch-mode DC to DC power supply designs have less than 100% conversion efficiency and provide an output voltage that has an error voltage characterized by a ripple voltage variation having a periodic amplitude variation from a target constant voltage level."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "Techniques for performing DC to DC power conversion in a switch-mode converter circuit include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The method includes operating the first phase switch circuit portion using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The method includes operating a second phase switch circuit portion using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number.

"In at least one embodiment of the invention, a method of operating a power converter circuit includes selectively disabling at least one switch device of a plurality of switch devices in a corresponding phase circuit of a plurality of phase circuits, at least partially based on a signal indicative of a load coupled to the power converter circuit. At least one switch device of the corresponding phase circuit is selectively disabled while at least one other switch device of the corresponding phase circuit is selectively enabled.

"In at least one embodiment of the invention, an apparatus includes a power converter circuit portion. The power converter circuit portion includes a first phase switch circuit portion configured to operate using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The first phase switch circuit portion is configured to operate using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The power converter circuit portion includes at least a second phase switch circuit portion configured to operate using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number.

BRIEF DESCRIPTION OF THE DRAWINGS

"The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

"FIG. 1 is a block diagram of a power converter circuit.

"FIG. 2 illustrates a system including an exemplary power converter circuit.

"FIG. 3 illustrates efficiency as a function of current for a power converter circuit consistent with FIG. 2.

"FIG. 4 illustrates a system including an exemplary power converter circuit consistent with at least one embodiment of the invention.

"FIG. 5 illustrates exemplary configurations of the exemplary power converter circuit of FIG. 4, consistent with at least one embodiment of the invention.

"FIG. 6 illustrates a system including an exemplary power converter circuit consistent with at least one embodiment of the invention.

"FIG. 7 illustrates exemplary configurations of the exemplary power converter circuit of FIG. 6, consistent with at least one embodiment of the invention.

"FIG. 8 illustrates exemplary information and control flows associated with the exemplary power converter circuit of FIG. 6, consistent with at least one embodiment of the invention.

"The use of the same reference symbols in different drawings indicates similar or identical items."

For more information, see this patent application: Hardman, Peter Thomas; Pang, Erwin; Lakhanpal, Sanjiv K. Asymmetric Topology to Boost Low Load Efficiency in Multi-Phase Switch-Mode Power Conversion. Filed April 10, 2014 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5628&p=113&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Advanced Micro Devices Inc.

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Source: Politics & Government Week


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