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"Integration of Shallow Trench Isolation and Through-Substrate Vias into Integrated Circuit Designs" in Patent Application Approval Process

August 28, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- A patent application by the inventors Bachman, Mark A. (Sinking Spring, PA); Merchant, Sailesh M. (Macungie, PA); Osenbach, John (Kutztown, PA), filed on April 11, 2014, was made available online on August 14, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to LSI Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Typical semiconductor integrated circuit (IC) designs require that some circuit components be electrically isolated from other circuit components within the design to avoid deleterious electrical interactions such as shorting or cross-talk. One method of isolating circuit components uses shallow trench isolation (STI) to separate these regions. Also in some IC designs, such as three-dimensional IC designs, through-substrate vias (TSV) are created connecting front-side circuitry to the substrate's back-side."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The present disclosure provides, in one embodiment, a method of manufacturing an integrated circuit. The method comprises providing a substrate having a first side and a second opposite side, forming a shallow trench isolation opening in the first side of the substrate and forming a partial through-substrate via opening in the first side of the substrate. The method also comprises extending the partial through-substrate-via opening, wherein the extended partial through-substrate-via opening is deeper into the substrate than the shallow trench isolation opening. The method further comprises filling the shallow trench isolation opening with a first solid material and filling the extended partial through-substrate via opening with a second solid material. Neither the shallow trench isolation opening, the partial through-substrate-via opening, nor the extended partial through-substrate-via opening penetrate an outer surface of the second side of the substrate. At least either: the shallow trench isolation opening and the partial through-substrate-via opening are formed simultaneously, or, the shallow trench isolation opening and the extended partial through-substrate-via opening are filled simultaneously.

"Another embodiment is another method of manufacturing an integrated circuit. The method comprises providing a substrate having a first side and a second opposite side. The method comprises forming a shallow trench isolation opening in the first side of the substrate. The method comprises forming a partial through-substrate via opening in the first side of the substrate, wherein the opening defining the shallow trench isolation structure and the opening defining the through-substrate via have a substantially same width-to-depth aspect ratio. The method comprises extending the partial through-substrate-via opening, wherein the extended partial through-substrate-via opening is deeper into the substrate than the shallow trench isolation opening. The method comprises filling the shallow trench isolation opening with a first solid material. The method comprises filling the extended partial through-substrate via opening with a second solid material. Neither the shallow trench isolation opening, the partial through-substrate-via opening, nor the extended partial through-substrate via penetrate an outer surface of the second side of the substrate. At least either: the shallow trench isolation opening and the partial through-substrate-via opening are formed simultaneously, or, the shallow trench isolation opening and the extended partial through-substrate-via opening are filled simultaneously.

"Still another embodiment of the disclosure is another method of manufacturing integrated circuit. The method comprises providing a substrate having a first side and a second opposite side. The method comprises forming a shallow trench isolation opening in the first side of the substrate. The method comprises forming a partial through-substrate via opening in the first side of the substrate. The method comprises extending the partial through-substrate-via opening, wherein the extended partial through-substrate-via opening is deeper into the substrate than the shallow trench isolation opening. The method comprises filling the shallow trench isolation opening with a first solid material. One end of the first material is buried inside the substrate and an opposite end of the first material is located at a surface of the first side of the substrate, and, the first sold material includes a passivation layer and a diffusion barrier layer on sidewalls of the opening defining the shallow trench isolation structure and on sidewalls of the opening defining the through-substrate via. The method comprises filling the extended partial through-substrate via opening with a second solid material. Neither the shallow trench isolation opening, the partial through-substrate-via opening, nor the extended partial through-substrate via penetrate an outer surface of the second side of the substrate. At least either: the shallow trench isolation opening and the partial through-substrate-via opening are formed simultaneously, or, the shallow trench isolation opening and the extended partial through-substrate-via opening are filled simultaneously.

BRIEF DESCRIPTION OF THE DRAWINGS

"For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

"FIG. 1 presents a flow diagram illustrating selective steps in an example embodiment of a method of manufacturing an integrated circuit of the disclosure;

"FIGS. 2-7 presents cross-sectional views of selected steps in an example method of manufacturing an example integrated circuit of the disclosure in accordance with the example method presented in FIG. 1; and

"FIG. 8 presents an example integrated circuit of the disclosure."

URL and more information on this patent application, see: Bachman, Mark A.; Merchant, Sailesh M.; Osenbach, John. Integration of Shallow Trench Isolation and Through-Substrate Vias into Integrated Circuit Designs. Filed April 11, 2014 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2866&p=58&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: LSI Corporation.

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Source: Politics & Government Week


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