News Column

Researchers Submit Patent Application, "Semiconductor Integrated Circuit Device", for Approval

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors HAYASHI, Kohtaro (Kyoto, JP); NISHIMURA, Hidetoshi (Osaka, JP), filed on April 8, 2014, was made available online on August 14, 2014.

The patent's assignee is Panasonic Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to a semiconductor integrated circuit device having standard cells (hereinafter simply referred to as cells as appropriate), and more particularly to a layout where a so-called multi-height cell is adjoined by another cell.

"A design method using standard cells is known as a method for designing a semiconductor integrated circuit. FIG. 20 is a layout example of a standard cell, where the dashed-dotted line defines the cell frame. The length of the standard cell in the Y direction (y1 in FIG. 20) is referred to as the cell height, and the length thereof in the X direction (x1 in FIG. 20) as the cell width. A cell having the same cell height as a reference height is referred to as a single-height cell. The cell width varies with the circuit configuration, or with the drive capability when the circuit configuration is same.

"In FIG. 20, a power supply interconnect 501 and a ground interconnect 506 formed in a metal interconnect layer are placed to extend from the right end to the left end of the cell frame along the top and bottom ends, respectively, of the cell. PMOS transistors MP51 to MP53 are formed in an N-well NW, and NMOS transistors MN51 to MN53 are formed in a P-well PW. A P+ diffusion interconnect 502 made of a P-type impurity diffusion region is placed to underlie the power supply interconnect 501 and connected to the power supply interconnect 501 via contacts 503. An N+ diffusion interconnect 507 made of an N-type impurity diffusion region is placed to underlie the ground interconnect 506 and connected to the ground interconnect 506 via contacts 508.

"In FIG. 20, also, P+ diffusion interconnects 504 and 505 branching from the P+ diffusion interconnect 502 are connected to source diffusion regions of the PMOS transistors MP51 to MP53, and N+ diffusion interconnects 509 and 510 branching from the N+ diffusion interconnect 507 are connected to source diffusion regions of the NMOS transistors MN51 to MN53. By contrast, FIG. 21 shows a layout configuration where diffusion interconnects 502A and 507A respectively placed under the power supply interconnect 501 and the ground interconnect 506 are used to fix the potentials of the wells NW and PW. The layouts in FIGS. 20 and 21 are well known as general layout configurations.

"In general, the area of a semiconductor integrated circuit can be reduced by reducing the cell height of standard cells. However, when a cell including a complicate circuit such as a flipflop circuit or a cell large in drive capability is prepared to have the reference cell height, the cell width of such a cell becomes very large, resulting in increasing the area instead of decreasing it, in some cases.

"For the above reason, there is known a technique of preparing such a cell as a multi-height cell having a cell height N times as large as the reference height (N is an integer equal to or more than 2). For example, a double-height cell having a cell height twice as large as the reference height has such a configuration that one of two single-height cells is inverted and such two single-height cells are integrated. A well having a height approximately twice as large as that of a well of a single-height cell is placed in the center portion of the cell in the cell height direction. Since transistors having a large gate width can be placed in such a well, a cell large in drive capability, for example, can be achieved.

"Japanese Unexamined Patent Publication No. H07-249747 and No. 2001-237328 describe semiconductor integrated circuit devices."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In recent semiconductor integrated circuit devices, a multi-height cell described above is often placed in addition to a single-height cell, and thus standard cells having different cell heights are present in a mixed manner. On the other hand, each standard cell used for design must have a layout configuration that obeys the design rules even when the standard cell is adjoined by any other standard cell on its top, bottom, right, or left side.

"FIG. 22 shows an example layout configuration where a single-height cell is placed to adjoin a double-height cell. CLa denotes the double-height cell, which has a P-well PW, an N-well NW and a P-well PW placed in this order from top in the cell height direction, and the height of the N-well NW in the center portion is twice as large as that of an N-well NW of the single-height cell. CLb denotes the single-height cell, which is placed so that the bottom end thereof is aligned with that of the cell CLa. That is, a ground interconnect 606 and an N+ diffusion interconnect 607 of the cell CLa are respectively connected to a ground interconnect 506 and an N+ diffusion interconnect 507 of the cell CLb. Also, the layout is designed in advance so that the spacing between the diffusion region of a transistor MP63a of the cell CLa and the diffusion region of a transistor MP51 of the cell CLb is equal to the minimum value SP under the separation rules. In other words, the diffusion regions of the transistors MP63a and MP51 are placed apart from the cell frame by 1/2 SP.

"In the N-well NW of the double-height cell CLa, since no diffusion interconnect is placed under a power supply interconnect 611, a large diffusion region is secured for transistors. In the layout in FIG. 22, a large transistor MP62 large in gate width and thus in drive capability is formed.

"In the single-height cell CLb, a P+ diffusion interconnect 502 extends to both ends of the cell frame along the top end. For this reason, in the double-height cell CLa, in order to obey the separation rules related to the P+ diffusion interconnect 502, a diffusion region formed in the N-well NW must be placed apart from the left end of the P+ diffusion interconnect 502 by the distance SP or more. Therefore, as for a gate interconnect GA63, the diffusion region must be divided into two in the cell height direction, and thus, failing to form a single transistor having a large gate width, two transistors MP63a and MP63b are formed. As for a gate interconnect GA61, also, the diffusion region is divided into two in the cell height direction, forming two transistors MP61a and MP61b.

"Note that the entire diffusion region in the N-well NW of the double-height cell CLa has a recess shape further deeper than by the distance SP from the P+ diffusion interconnect 502 in FIG. 22. The reason for this is that there is also a limitation under the design rules related to the minimum size of the diffusion region relative to the gate electrode of a transistor.

"As described above, in the wide well in the center portion of the double-height cell, the transistors placed near both ends in the cell width direction are not allowed to secure a sufficiently large gate width under the design rules in consideration of the layout configuration of an adjoining cell. Therefore, improvement in the drive capability of transistors, which is one of the objectives for using a double-height cell, cannot be necessarily sufficiently achieved. In particular, in order for a PMOS transistor, which is low in current capability, to secure large drive capability with a small area, it is desirable to form a transistor having a large gate width by making full use of the region available for formation of PMOS transistors.

"In addition, in a microfabrication process, in order to prevent or reduce variations in the shape of gate electrodes of transistors, a dummy gate is sometimes placed on a cell boundary to ensure placement of gate electrodes at an equal pitch. For example, in FIG. 22, it is necessary to place a dummy gate on the cell boundary at the same pitch as the gates GA61 to GA63. However, if a dummy gate is placed on the cell boundary in the layout in FIG. 22, an unnecessary transistor will be formed by the P+ diffusion interconnect 502 and the dummy gate.

"The problem described above is not limited to the double-height cell, but can arise in a multi-height cell having a layout configuration where a wide well is formed and a diffusion interconnect of another cell can adjoin the well.

"It is an objective of the present disclosure to provide a layout configuration of a semiconductor integrated circuit device where a multi-height cell is adjoined by another cell, where improvement in the drive capability of transistors in the multi-height cell can be sufficiently achieved.

"According to an aspect of the present disclosure, a semiconductor integrated circuit device where a plurality of cells are placed is provided, the plurality of cells including: a first cell that is a multi-height cell having a cell height N times as large as a reference cell height (N is an integer equal to or more than 2); and a second cell placed to adjoin the first cell in a cell width direction, wherein the second cell includes a first metal interconnect placed to extend in the cell width direction along one end in a cell height direction, and a first diffusion interconnect that is made of an impurity diffusion region formed to extend under the first metal interconnect in the cell width direction and connected to the first metal interconnect via contacts, the first cell includes a first transistor diffusion region that is opposed to the first diffusion interconnect in the cell width direction, is formed to stride across, in the cell height direction, a region extended in the cell width direction of the first metal interconnect, and constitutes a transistor, and the first diffusion interconnect is placed apart from a cell boundary between the first cell and the second cell in the cell width direction.

"According to the aspect described above, the second cell placed to adjoin the first cell that is a multi-height cell includes a first metal interconnect extending in the cell width direction along one end in the cell height direction and a first diffusion interconnect made of an impurity diffusion region formed to extend under the metal interconnect in the cell width direction. The first cell includes a first transistor diffusion region formed to stride across, in the cell height direction, a region extended in the cell width direction of the first metal interconnect of the second cell. The first diffusion interconnect of the second cell opposed to the first transistor diffusion region is apart from the cell boundary between the first cell and the second cell in the cell width direction. This ensures obedience of the separation rules related to the spacing between the first transistor diffusion region of the first cell and the diffusion interconnect of the second cell, eliminating the necessity of dividing the first transistor diffusion region into parts. Therefore, a transistor large in gate width can be formed even near another cell placed adjacently without being affected by the layout of the cell.

"According to the present disclosure, in a multi-height cell, a transistor large in gate width can be formed even near another cell placed adjacently. Thus, the drive capability of a transistor in a multi-height cell can be improved compared with that conventionally achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a plan view showing a layout configuration of a single-height cell in the first embodiment.

"FIG. 2 is a plan view showing a layout configuration of a double-height cell in the first embodiment.

"FIG. 3 is a plan view showing a layout configuration of a semiconductor integrated circuit device of the first embodiment.

"FIG. 4 is a plan view showing a layout configuration of a single-height cell in the second embodiment.

"FIG. 5 is a plan view showing a layout configuration of a double-height cell in the second embodiment.

"FIG. 6 is a plan view showing a layout configuration of a semiconductor integrated circuit device of the second embodiment.

"FIG. 7 is a plan view showing a layout configuration of the semiconductor integrated circuit device of the second embodiment.

"FIG. 8 is a plan view showing another example of the layout configuration of the semiconductor integrated circuit device of the second embodiment.

"FIG. 9 is a view showing part of a design flow of a semiconductor integrated circuit device of the third embodiment.

"FIG. 10 is a view showing design data of a single-height cell in the third embodiment.

"FIG. 11 is a view showing design data of a double-height cell in the third embodiment.

"FIG. 12 shows an example of layout design data created in a layout design step S11 in FIG. 9.

"FIG. 13 is a plan view showing a layout configuration of the semiconductor integrated circuit device of the third embodiment.

"FIG. 14 shows an example of layout design data created in the layout design step S11 in FIG. 9.

"FIG. 15 is a plan view showing a layout configuration of the semiconductor integrated circuit device of the third embodiment.

"FIG. 16 is a view showing design data of a single-height cell in the fourth embodiment.

"FIG. 17 is a view showing design data of a double-height cell in the fourth embodiment.

"FIG. 18 is a plan view showing a layout configuration of a semiconductor integrated circuit device of the fourth embodiment.

"FIG. 19 is a plan view showing another example of the layout configuration of a single-height cell in an embodiment.

"FIG. 20 is a plan view showing a layout configuration of a general single-height cell.

"FIG. 21 is a plan view showing a layout configuration of another general single-height cell.

"FIG. 22 is a view for explaining a problem to be solved by the present disclosure."

For additional information on this patent application, see: HAYASHI, Kohtaro; NISHIMURA, Hidetoshi. Semiconductor Integrated Circuit Device. Filed April 8, 2014 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6112&p=123&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Electronics, Semiconductor, Panasonic Corporation.

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Source: Electronics Newsweekly


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