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Researchers Submit Patent Application, "Processing System for Combined Metal Deposition and Reflow Anneal for Forming Interconnect Structures", for...

August 27, 2014



Researchers Submit Patent Application, "Processing System for Combined Metal Deposition and Reflow Anneal for Forming Interconnect Structures", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Yang, Chih-Chao (Glenmont, NY); Cohen, Stephan A. (Wappingers Falls, NY); Maniscalco, Joseph F. (Lake Katrine, NY), filed on February 5, 2013, was made available online on August 14, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to semiconductor device manufacturing. More particularly, the present disclosure relates to a method of forming an interconnect structure in which the interconnect conductive metal is formed by deposition of a metal liner and a reflow anneal which are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. The present disclosure also provides a multi-chambered processing system in which the deposition and reflow anneal can be performed without breaking vacuum between the two processing steps.

"Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene interconnect structures. The interconnect structure typically includes copper, Cu, or a Cu alloy since Cu-based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al,-based interconnects.

"Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as 'crosstalk') is achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.

"During the formation of interconnect structures, the interconnect conductive metal, i.e., copper, is typically formed within an opening, e.g., line and/or via, which is present in an interconnect dielectric material, using a wet electrical-chemical plating (ECP) process. Prior to the ECP process, the open features are lined with a barrier liner and copper seed layer through a dry deposition process, e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The ECP process is problematic from a chemical perspective. For example, the impurity levels in electroplated copper used for interconnect structures are: carbon, 100 parts per million (ppm), chlorine, 80 ppm, oxygen, 80 ppm, and sulfur, 50 ppm. At these impurity levels the conductivity of the copper interconnect can degrade beyond acceptable levels. Also, two different deposition steps, dry metal seed layer formation and wet ECP, are needed in the conventional processes flow which increase the time and cost of forming the interconnect structures.

"In addition, and when small feature sizes (on the order of 50 nm or less) are subjected to the conventional processes, a portion of the opening that is formed into the interconnect dielectric material may remain unfilled. This may cause performance degradation as well as reliability related issues. As such, a method is needed that overcomes the above problems associated with ECP processes."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "An interconnect conductive metal used in forming an interconnect structure can be formed using a method in which deposition of a metal liner and a reflow anneal are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. In the disclosure, an interconnect dielectric material including an opening is placed within the multi-chambered processing system and then the interconnect dielectric material is transferred, under vacuum, to a deposition chamber in which the metal liner is deposited. The interconnect dielectric material including the metal liner is then transferred, under the same vacuum, to an annealing chamber in which a reflow anneal is performed.

"In one aspect of the present disclosure, a method for forming an interconnect structure is provided. The method of the present disclosure includes providing an interconnect dielectric material having at least one opening. The interconnect dielectric material having the at least one opening is then placed within a multi-chambered processing system. Next, at least a metal liner comprising a conductive metal or conductive metal alloy is deposited above an uppermost surface of the interconnect dielectric material and in the at least one opening. In accordance with the present disclosure, the depositing of at least the metal liner is performed in a deposition chamber of the multi-chambered processing system. A reflow anneal is then performed within an annealing chamber of the multi-chambered processing system. In accordance with the present disclosure, the reflow anneal flows a portion of the metal liner located above the uppermost surface of the interconnect dielectric material into the at least one opening and fills the at least one opening with the conductive metal or conductive metal alloy. In accordance with the method of the present disclosure, a continuous vacuum is maintained during the depositing and the reflow anneal.

"In another embodiment of the present disclosure, a processing system for forming interconnect structures is provided. The processing system of the present disclosure includes a loading/unloading chamber and a transfer chamber coupled to at least one deposition chamber and at least one annealing chamber, wherein the at least one deposition chamber is configured to deposit at least a metal liner comprising a conductive metal or conductive metal alloy above an uppermost surface of an interconnect dielectric material and in at least one opening present in the interconnect dielectric material, and the annealing chamber is configured to reflow the metal liner on the uppermost surface of the interconnect dielectric material and to fill the at least one opening with the conductive metal or conductive metal alloy. In accordance with the present disclosure, the processing system is configured to maintain a continuous vacuum during the depositing and reflow process.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a pictorial representation (through a cross sectional view) illustrating an initial structure including an interconnect dielectric material that can be employed in one embodiment of the present disclosure.

"FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the initial structure of FIG. 1 after forming an opening in the interconnect dielectric material.

"FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of FIG. 2 after forming a diffusion barrier on exposed surfaces of the interconnect dielectric material.

"FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of FIG. 3 after forming a metal liner comprising a conductive metal or conductive metal alloy on the diffusion barrier.

"FIG. 5 is a pictorial representation (through a cross sectional view) illustrating the structure of FIG. 4 after formation of an interconnect conductive metal by performing a reflow anneal on the structure of FIG. 4 including the metal liner.

"FIG. 6 is a schematic illustrating a top view diagram of a simplistic multi-chambered processing system that can be used in the present disclosure for forming at least the interconnect conductive metal shown in FIG. 5.

"FIG. 7 is a schematic illustrating a top down diagram of a multi-chambered processing system that can be used in the present disclosure for depositing of the metal liner and performing the reflow anneal.

"FIG. 8 is a flow diagram of one embodiment of the present disclosure for forming an interconnect structure using the multi-chambered processing system shown in FIG. 7.

"FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the structure of FIG. 5 after performing a planarization process."

For additional information on this patent application, see: Yang, Chih-Chao; Cohen, Stephan A.; Maniscalco, Joseph F. Processing System for Combined Metal Deposition and Reflow Anneal for Forming Interconnect Structures. Filed February 5, 2013 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2849&p=57&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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