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Researchers Submit Patent Application, "Methods for Optical Proximity Correction in the Design and Fabrication of Integrated Circuits", for Approval

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Lukanc, Todd (San Jose, CA); Clifford, Christopher Heinz (San Francisco, CA); Coskun, Tamer (San Jose, CA), filed on February 1, 2013, was made available online on August 14, 2014.

The patent's assignee is Globalfoundries, Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Generally, integrated circuits and other semiconductor devices are used in a variety of electronic applications, such as computers, cellular phones, personal computing devices, and many other applications. Home, industrial, and automotive devices, which in the past included only mechanical components, now have electronic parts that require semiconductor devices.

"Semiconductor devices are manufactured by depositing many different types of material layers over a semiconductor workpiece or wafer, and patterning the various material layers using lithography. The material layers typically include thin films of conductive, semiconductive, and insulating materials that are patterned and etched to form integrated circuits (IC's). There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single die or chip.

"Lithography involves the transfer of an image of a mask to a material layer of a die or chip, also referred to as a wafer. The image is formed in a layer of photoresist, the photoresist is developed, and the photoresist is used as a mask during a process to alter the material layer, such as etching and patterning the material layer.

"As feature sizes of semiconductor devices continue to decrease, as is the trend in the semiconductor industry, transferring patterns from a lithography mask to a material layer of a semiconductor device becomes more difficult, due to the effects of the light or energy used to expose the photoresist. A phenomenon referred to as the 'proximity effect' results in the line width of patterns varying, depending the proximity of a feature to other features. Closely-spaced features tend to be smaller than widely-spaced features, although on a lithography mask they include the same dimensions. It is important in many semiconductor device designs for features to have uniform, predictable dimensions across a surface of a wafer to achieve the required device performance.

"To compensate for the proximity effect, optical proximity corrections (OPC) are often made to lithography masks, which may involve adjusting the widths or lengths of the lines on the mask. More advanced methods of OPC correct corner rounding and a general loss of fidelity in the shape of features by adding small secondary patterns referred to as serifs to the corners of patterns. The serifs, together with line width changes, enhance the amount of light transmitted through the transparent mask patterns.

"The OPC design phase is time-consuming, and therefore costly. Often, it is desirable to introduce a product as quickly as possible to the market in the semiconductor device industry. However, it may take up to two or three weeks for OPC calculations to be performed on a semiconductor device design.

"As such, it is desirable to provide faster and more efficient methods of calculating and determining OPC for lithography masks used to fabricate semiconductor devices. Furthermore, other desirable features and characteristics of the inventive subject matter will become apparent from the subsequent detailed description of the inventive subject matter and the appended claims, taken in conjunction with the accompanying drawings and this background of the inventive subject matter."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Methods for optical proximity correction in the design of integrated circuits are disclosed. In an exemplary embodiment, a method of manufacturing an optical lithography mask includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate. The step of designing the optical photomask includes providing a patterned layout design comprising a plurality of polygons that correspond with the pre-pattern opening, correcting the patterned layout design using optical proximity correction by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design. In an alternative embodiment, biasing may be provided by altering the light during mask write of the plurality of polygons. The method further includes manufacturing the optical photomask in a mask writer tool using the biased, mask writer-compatible layout design as a template for the optical photomask.

"In accordance with another exemplary embodiment, a method for fabricating an integrated circuit includes providing semiconductor substrate comprising a silicon material, forming a photoresist layer over the semiconductor substrate, and providing an optical photomask mask. Providing the optical lithography mask includes the step of designing the optical photomask for forming a pre-pattern opening in the photoresist layer on the semiconductor substrate. The step of designing the optical photomask includes providing a patterned layout design comprising a plurality of polygons that correspond with the pre-pattern opening, correcting the patterned layout design using optical proximity correction by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design. Providing the optical lithography mask further includes the step of manufacturing the optical photomask in a mask writer tool using the biased, mask writer-compatible layout design as a template for the optical photomask. In an alternative embodiment, biasing may be provided by altering the light during mask write of the plurality of polygons. The method further comprises disposing the optical photomask over the photoresist layer and directing a light source through the photomask so as to expose a portion of the photoresist layer to the light source.

"This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

"A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.

"FIG. 1 is a block diagram of a process for optical proximity correction known in the aft.

"FIG. 2 is a block diagram of an exemplary process for optical proximity correction in accordance with an embodiment of the present disclosure.

"FIG. 3 is a schematic illustration of a block diagram of a computing system arranged in accordance with some examples."

For additional information on this patent application, see: Lukanc, Todd; Clifford, Christopher Heinz; Coskun, Tamer. Methods for Optical Proximity Correction in the Design and Fabrication of Integrated Circuits. Filed February 1, 2013 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2840&p=57&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Electronics, Semiconductor, Globalfoundries Inc..

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Source: Electronics Newsweekly


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