The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly-doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
"The drive for high performance requires high-speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current of the transistor adversely impact leakage current.
"Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high-temperature annealing to activate the source/drain implants, such as at temperatures in excess of 900.degree.
"Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
"Additional issues arise with lateral scaling, such as the formation of contacts. For example, once the contacted gate pitch gets to about 64 nanometers (nm), there is not enough room to land a contact between the gate lines and still maintain reliable electrical isolation properties between the gate line and the contact. Self-aligned contact (SAC) methodology has been developed to address this problem. Conventional SAC approaches involve recessing the replacement metal gate structure, which includes both workfunction metal liners (e.g. TiN, TaN, TaC, TiC, TiAlN, etc.) and a conducting metal (e.g., W, Al, etc.), followed by a dielectric cap material deposition and chemical mechanical planarization (CMP). However, to set the correct workfunction for the device, sometimes thick work function metal liners are required (e.g., a combination of different metals such as TiN, TiC, TaC, TiC, or TiAlN with a total thickness of more than 7 nm). As gate length continues to scale down, for example for sub-15 nm gates, the replacement gate structure is so narrow that it will be 'pinched-off' by the work function metal liners alone, with little or no space remaining for the lower-resistance gate metal. This will cause high resistance issue for devices with small gate lengths, and will also cause problems in the SAC replacement gate metal recess.
"Accordingly, it is desirable to provide methods for the fabrication of integrated circuits that integrate both metal replacement gates and self-aligned contacts with workfunction metal liner compatibility. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings, the brief summary, and this background of the invention."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Methods of manufacturing integrated circuits having replacement metal gate structures, and the integrated circuits formed thereby, are disclosed herein. In accordance with an exemplary embodiment, a method of fabricating an integrated circuit includes the steps of forming an interlayer dielectric (ILD) layer over a dummy gate stack. The dummy gate stack is formed over a semiconductor substrate. The dummy gate stack includes a dummy gate structure, a hardmask disposed over the dummy gate structure, and sidewall spacers disposed along sides of the dummy gate structure and the hardmask. The method further includes removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer, forming a thin liner along the ILD layer within the first opening, extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack, thereby exposing a portion of the semiconductor substrate, and depositing at least one workfunction material layer within the first opening and within the first extended opening. Still further, the method includes removing portions of the workfunction material within the first opening and depositing a low-resistance material over a remaining portion of the workfunction material thereby forming a replacement metal gate structure that includes the remaining portion of the workfunction material and the low-resistance material.
"In accordance with another exemplary embodiment, an integrated circuit includes a semiconductor substrate and first and second sidewall spacers formed over the semiconductor substrate. The first and second sidewall spacers have a first height and are separated from one another by a space. The integrated circuit further includes at least one layer of a workfunction material disposed in the space. The at least one layer of the workfunction material is deposited to a second height that is at least as high as the first height. Still further, the integrated circuit includes a low-resistance material formed over the at least one layer of the workfunction material.
"In accordance with yet another exemplary embodiment, a method of fabricating an integrated circuit includes forming an interlayer dielectric (ILD) layer over a dummy gate stack. The dummy gate stack is formed over a semiconductor substrate and a dummy oxide layer is formed over the semiconductor substrate. The dummy gate stack includes a dummy gate structure, a hardmask disposed over the dummy gate structure, and sidewall spacers disposed along sides of the dummy gate structure and the hardmask and over the dummy oxide layer. The method further includes removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer. This step of removing at least the upper portion includes removing the hardmask and portions of the sidewall spacers adjacent to the hardmask. The method further includes forming a thin silicon nitride liner along the ILD layer within the first opening, extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack and a portion of the dummy oxide layer disposed thereunder, thereby exposing a portion of the semiconductor substrate, and depositing a layer of a first workfunction material and a layer of a second workfunction material within the first opening and within the first extended opening. Still further, the method includes depositing an organic planarization layer within the first opening, removing portions of the first and second workfunction material layers within the first opening, using the organic planarization layer as an etch mask, removing the organic planarization layer, re-forming a portion of the sidewall spacers, and depositing a low-resistance tungsten material over a remaining portion of the workfunction material layers and in between the re-formed portion of the sidewall spacers, thereby forming a replacement metal gate structure that includes the remaining portion of the workfunction material and the low-resistance material. The method optionally includes forming a capping layer over the replacement metal gate structure.
"This brief summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
BRIEF DESCRIPTION OF THE DRAWINGS
"The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
"FIG. 1 is a flowchart illustrating a method for fabricating an integrated circuit having a replacement gate structure in accordance with one embodiment of the present disclosure;
"FIGS. 2-13 are partial cross-sectional views of a partially-formed integrated circuit illustrating certain aspects of the method of FIG. 1 for fabricating an integrated circuit having a replacement gate structure."
For additional information on this patent application, see: Xie, Ruilong; Cai, Xiuyu; Cheng, Kangguo; Khakifirooz, Ali. Integrated Circuits Having Replacement Gate Structures and Methods for Fabricating the Same. Filed
Keywords for this news article include: Electronics, Semiconductor, Microtechnology,
Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC
Most Popular Stories
- Doctor Who Christmas Episode Begins Production
- HCL America Adding 1,200 IT Jobs
- Medical Mfg. Jobs Coming to Dayton
- Michael Jackson, Freddie Mercury on Previously Unreleased Queen Cut
- Longtime Unemployed to Get Help in Las Vegas
- SpaceX Aims for Predawn Launch on Saturday
- Women Key to Democratic Party: Clinton
- U.S. Chamber Caught Up in Tax Inversion Question
- Feds Won't Say How Many Border Crossers Jailed
- Christie Didn't Order Bridge Shut Down, Feds Say