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Researchers Submit Patent Application, "Equalizer and Semiconductor Memory Device Including the Same", for Approval

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors KIM, Dae-Hyun (Hwaseong-si, KR); BAE, Seung-Jun (Hwaseong-si, KR); HA, Kyung-Soo (Hwaseong-si, KR), filed on January 28, 2014, was made available online on August 14, 2014.

The patent's assignee is Samsung Electronics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "This disclosure relates to an equalizer and a semiconductor memory device including the same, and more particularly, to an equalizer having a reduced layout area and a semiconductor memory device including the same.

"A plurality of tri-state buffers for sequentially outputting data are used at an internal or external node of a semiconductor memory device, such as DRAM or flash memory. The plurality of tri-state buffers may have a high impedance state during an operation. As the plurality of tri-state buffers are in a high impedance state, when an output node floats, a semiconductor memory device may operate unstably. Moreover, when a semiconductor memory device operates at high speed, intersymbol interference (ISI) may occur in an output signal of a tri-state buffer."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The disclosed embodiments provide an equalizer having a reduced layout area.

"The disclosed embodiments provide a semiconductor memory device including the equalizer for stably and accurately outputting data.

"According to one embodiment, there is provided an equalizer including a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit coupled to the delay circuit and configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.

"According to one embodiment, there is provided a semiconductor memory device including a multiplexer and an equalizer. The multiplexer includes a plurality of tri-state buffers and is configured to sequentially output a plurality of data signals corresponding to a respective plurality of data signals applied in parallel to the plurality of tri-state buffers. The equalizer includes an input/output node connected to an output node of the multiplexer, and is configured to operate as an inductive bias circuit amplifying the output signal of the multiplexer and outputting the amplified output signal, and to operate as a latch circuit storing and outputting an output signal of the multiplexer, in response to a select signal.

"According to one embodiment, there is provided a memory device including a first and second driver circuits. The first driver circuit is configured to output one or more output signals on an output node of the first driver circuit or float the output node based on a first driver select signal. The second driver circuit is configured to amplify or store the one or more output signals in response to a second driver select signal, and to store the one or more output signals when the first driver circuit is deactivated.

BRIEF DESCRIPTION OF THE DRAWINGS

"Exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

"FIG. 1 is a block diagram of an equalizer according to exemplary embodiments;

"FIG. 2 is an exemplary circuit diagram illustrating the equalizer of FIG. 1 according to one embodiment;

"FIGS. 3A to 3D are an exemplary circuit diagram and timing diagram illustrating that the equalizer of FIG. 1 operates as an inductive bias circuit according to one embodiment;

"FIG. 4 is an exemplary circuit diagram illustrating that the equalizer of FIG. 1 operates as a latch circuit according to one embodiment;

"FIG. 5 is an exemplary circuit diagram illustrating the equalizer of FIG. 1 according to another embodiment;

"FIG. 6 is an exemplary block diagram of an equalizer according to another embodiment;

"FIG. 7 is an exemplary circuit diagram illustrating the equalizer of FIG. 6 according to one embodiment;

"FIG. 8 is an exemplary block diagram illustrating the equalizer of FIG. 1 and a multiplexer according to one embodiment;

"FIG. 9 is an exemplary circuit diagram illustrating a tri-state buffer;

"FIG. 10 is an exemplary block diagram illustrating the equalizer of FIG. 6 and a multiplexer according to one embodiment;

"FIG. 11 is an exemplary block diagram illustrating a semiconductor memory device according to certain embodiments;

"FIG. 12 is an exemplary view illustrating a structure of a semiconductor memory device according to certain embodiments;

"FIG. 13 is an exemplary view illustrating a memory system including a semiconductor memory device, according to embodiments;

"FIG. 14 is an exemplary view illustrating a structure of a server system including a semiconductor memory device, according to certain embodiments;

"FIG. 15 is an exemplary view illustrating a semiconductor memory system including an SSD as a semiconductor memory device, according to certain embodiments; and

"FIG. 16 is an exemplary view illustrating a computer system including a semiconductor memory device, according to certain embodiments."

For additional information on this patent application, see: KIM, Dae-Hyun; BAE, Seung-Jun; HA, Kyung-Soo. Equalizer and Semiconductor Memory Device Including the Same. Filed January 28, 2014 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4590&p=92&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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