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Researchers Submit Patent Application, "Compound Semiconductor Device and Method for Manufacturing the Same", for Approval

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor YAMADA, Atsushi (Kawasaki, JP), filed on April 11, 2014, was made available online on August 14, 2014.

The patent's assignee is Fujitsu Limited.

News editors obtained the following quote from the background information supplied by the inventors: "A nitride semiconductor device is under active development for use as a semiconductor device with high-voltage resistance and high output, by making use of the feature of a high saturation electron speed, a wide band gap and the like. As for the nitride semiconductor device, there have been a large number of reports on a field effect transistor, and particularly on a high electron mobility transistor (HEMT). In particular, an AlGaN/GaN-HEMT has received attention, which uses GaN as an electron transit layer and AlGaN as an electron supply layer. In the AlGaN/GaN-HEMT, distortion occurs in AlGaN, which originates in the difference between the lattice constants of GaN and AlGaN. A high concentration of two-dimensional electron gas (2D EG) is obtained due to the piezo polarization generated by the distortion and the spontaneous polarization of AlGaN. Because of this, high-voltage resistance and a high output can be realized."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "One embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor layer formed above the substrate; a gate electrode formed above the compound semiconductor layer; a gate pad that is formed above the compound semiconductor layer and has a current path formed between the gate electrode and itself; a semiconductor layer that is formed above the compound semiconductor layer and is spontaneously polarized; and a gate connection layer formed on the semiconductor layer, wherein the gate connection layer and the gate electrode are electrically connected with each other.

"One embodiment of a method for manufacturing a compound semiconductor device includes: forming a compound semiconductor layer above a substrate; forming a gate electrode above the compound semiconductor layer; forming a gate pad that has a current path formed between the gate electrode and itself, above the compound semiconductor layer; forming a semiconductor layer that is spontaneously polarized, above the compound semiconductor layer; and forming a gate connection layer on the semiconductor layer, wherein the gate connection layer and the gate electrode are electrically connected with each other.

"The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

"It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.

BRIEF DESCRIPTION OF DRAWINGS

"FIG. 1 is a plan view illustrating a schematic structure of a compound semiconductor device according to a first embodiment;

"FIG. 2A is a schematic sectional view illustrating a method for manufacturing a compound semiconductor device according to the first embodiment;

"FIG. 2B is a schematic sectional view which follows FIG. 2A and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 2C is a schematic sectional view which follows FIG. 2B and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 2D is a schematic sectional view which follows FIG. 2C and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 2E is a schematic sectional view which follows FIG. 2D and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 2F is a schematic sectional view which follows FIG. 2E and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 2G is a schematic sectional view which follows FIG. 2F and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 2H is a schematic sectional view which follows FIG. 2G and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 2I is a schematic sectional view which follows FIG. 2H and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 2J is a schematic sectional view which follows FIG. 2I and illustrates the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 3A is a schematic sectional view illustrating a part of steps in the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 3B is a schematic sectional view illustrating a part of steps in the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 3C is a schematic sectional view illustrating a part of steps in the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 4 is a schematic sectional view illustrating a part of steps in the method for manufacturing the compound semiconductor device according to the first embodiment;

"FIG. 5 is a schematic sectional view illustrating an AlGaN/GaN-HEMT of a comparative example;

"FIG. 6A is a schematic sectional view for describing a function and an effect of the AlGaN/GaN-HEMT according to the first embodiment;

"FIG. 6B is a schematic sectional view for describing a function and an effect of the AlGaN/GaN-HEMT according to the first embodiment;

"FIG. 7A is a view illustrating a band diagram of an AlGaN/GaN-HEMT according to a comparative example of the first embodiment;

"FIG. 7B is a view illustrating a band diagram of an AlGaN/GaN-HEMT according to the first embodiment;

"FIG. 8 is a characteristic diagram illustrating drain current-gate voltage characteristics in the AlGaN/GaN-HEMTs according to the first embodiment and the comparative example;

"FIG. 9 is a schematic sectional view illustrating a compound semiconductor device of a modified example of the first embodiment;

"FIG. 10A is a schematic sectional view illustrating a principal step in a method for manufacturing a compound semiconductor device according to a second embodiment;

"FIG. 10B is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the second embodiment;

"FIG. 10C is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the second embodiment;

"FIG. 11 is a schematic sectional view illustrating a compound semiconductor device of a modified example of the second embodiment;

"FIG. 12A is a schematic sectional view illustrating a principal step in a method for manufacturing a compound semiconductor device according to a third embodiment;

"FIG. 12B is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the third embodiment;

"FIG. 12C is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the third embodiment;

"FIG. 12D is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the third embodiment;

"FIG. 13 is a schematic sectional view illustrating a compound semiconductor device of a modified example of the third embodiment;

"FIG. 14A is a schematic sectional view illustrating a principal step in a method for manufacturing a compound semiconductor device according to a fourth embodiment;

"FIG. 14B is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the fourth embodiment;

"FIG. 14C is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the fourth embodiment;

"FIG. 14D is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the fourth embodiment.

"FIG. 14E is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the fourth embodiment;

"FIG. 15 is a schematic sectional view illustrating a compound semiconductor device of a modified example of the fourth embodiment;

"FIG. 16A is a schematic sectional view illustrating a principal step in a method for manufacturing a compound semiconductor device according to a fifth embodiment;

"FIG. 16B is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the fifth embodiment;

"FIG. 16C is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the fifth embodiment;

"FIG. 16D is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the fifth embodiment;

"FIG. 16E is a schematic sectional view illustrating a principal step in the method for manufacturing the compound semiconductor device according to the fifth embodiment;

"FIG. 17 is a connection wiring diagram illustrating a schematic structure of a power-supply unit according to a six embodiment; and

"FIG. 18 is a connection wiring diagram illustrating a schematic structure of a high-frequency amplifier according to a seventh embodiment."

For additional information on this patent application, see: YAMADA, Atsushi. Compound Semiconductor Device and Method for Manufacturing the Same. Filed April 11, 2014 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4634&p=93&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Electronics, High Voltage, Semiconductor, Fujitsu Limited.

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Source: Electronics Newsweekly


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