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Patent Issued for Transmission and Receiving Apparatus and Method Having Different Sending and Receiving Clocks

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventor Uehara, Teruaki (Kanagawa, JP), filed on October 5, 2010, was published online on August 12, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8804887 is assigned to LAPIS Semiconductor Co., Ltd. (Tokyo, JP).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method having a so-called metastability measure.

"An apparatus such as, for example, a personal computer or a server often employs a configuration with a circuit responsible for general-purpose operations incorporated into a semiconductor chip and a circuit specific to each user incorporated into FPGA (field programmable gate array) such that the apparatus is operated by mutually sending and receiving signals between the semiconductor chip and the FPGA from a cost standpoint.

"Such a configuration produces a problem of a signal transmission method between the semiconductor chip and the FPGA. Since the operation clock frequency of the semiconductor chip is typically different from the operation clock frequency of the FPGA, it is problematic that a receiving flip-flop oscillates (a so-called metastable phenomenon occurs) depending on signal acquisition timing on the reception side. That is, if a signal level is changed at the timing of signal acquisition by the receiving flip-flop, it is not determined whether the signal level is high or low, resulting in oscillation of the receiving flip-flop.

"A circuit with a few flip-flops connected in series is conventionally used as a so-called metastability measure for preventing this oscillation phenomenon (see, e.g., Japanese Patent Kokai No. 2008-242527). FIG. 1 is a block diagram of a conventional metastability measure circuit 400. The metastability measure circuit 400 consists of a first flip-flop 410 and a second flip-flop 420 mutually connected in series. The first flip-flop 410 acquires in synchronization with a receiving clock RC a signal DI changing in level in synchronization with a sending clock to retain the signal. The second flip-flop 420 acquires the signal level retained by the first flip-flop 410 in synchronization with the receiving clock RC to retain and output the signal level as a signal DO having the signal level retained by the second flip-flop 420. In such a configuration, even when the first flip-flop 410 is in the oscillating state, the second flip-flop 420 stably acquires a signal level after the oscillation has converged. Therefore, the output of the signal DO is stabilized. Such a metastability measure using a few flop-flops is often used in a transmission apparatus for transmitting a control signal.

"However, such a conventional metastability measure circuit has the following problems. A first problem is that a control signal pulse is unable to be received correctly on the reception side. The control signal is often sent and received as a pulse with one clock width. In this case, for example, if the frequency of the operation clock on the reception side is lower than the frequency of the operation clock on the transmission side, the control signal pulse cannot be acquired on the reception side, resulting in so-called control signal pulse loss. On the other hand, if the frequency of the operation clock on the transmission side is lower than the frequency of the operation clock on the reception side, one control signal pulse is acquired for a plurality of times on the reception side, leading to the operation same as the case of receiving a plurality of control signal pulses. Therefore, even the usage of the conventional metastability measure circuit cannot solve the problem generated because the operation clock frequencies are different between the transmission side and the reception side.

"A second problem is a delay of the control signal. The frequency of the operation clock of FPGA is typically lower than the frequency of the operation clock of a semiconductor chip. If the conventional metastability measure circuit is used when FPGA is on the reception side, a delay of the control signal received by the FPGA increases within the circuit. If the conventional metastability measure circuit is used, a delay of two cycles of the operation clock is generated between reception and output of the control signal by the FPGA. If the frequency of the operation clock of the FPGA is lower, the delay of two cycles is a considerable delay."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "The present invention has been made in view of the problems described above and it is therefore an object of the present invention to provide a transmission apparatus, a signal sending apparatus, a signal receiving apparatus, a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example.

"A transmission apparatus according to the present invention is a transmission apparatus transmitting a signal, comprising a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period; and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.

"A signal sending apparatus according to the present invention is a signal sending apparatus operating in synchronization with a clock having a predetermined period to output a transmission signal in response to an input of a pulse signal corresponding to the predetermined period, comprising a first signal generating part that inverts a signal level of the transmission signal in synchronization with a rising edge of the clock after the input of the pulse signal; a second signal generating part that inverts a signal level of the transmission signal in synchronization with the input of the pulse signal; and an output selecting part that selects an output of the first signal generating part when the predetermined period is shorter than a period of a receiving clock and selects an output of the second signal generating part when the first period is longer than the period of the receiving clock.

"A signal receiving apparatus according to the present invention is a signal receiving apparatus operating in synchronization with a clock having a predetermined period to receive a transmission signal, comprising a first level retaining part that retains a signal level of the transmission signal at a rising edge of the clock as well as at a falling edge of the clock; a first selecting part that selects and outputs one of two signal levels retained by the first level retaining part; a second level retaining part that retains an output of the first selecting part at a rising edge of the clock as well as at a falling edge of the clock; a second selecting part that selects and outputs one of two signal levels retained by the second level retaining part; a preceding level retaining part that retains an output of the second selecting part at a rising edge of the second clock; and an EXOR circuit part that inputs the output of the second selecting part and an output of the preceding level retaining part to generate and output a pulse signal from an exclusive logical sum of the two outputs.

"A transmission method according to the present invention is a transmission method of transmitting a signal, comprising a sending step of outputting in synchronization with a first clock having a first period a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period; and a receiving step of outputting in synchronization with a second clock having a second period a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.

"A signal sending method according to the present invention is a transmission method of outputting in synchronization with a clock having a predetermined period a transmission signal in response to an input of a pulse signal corresponding to the predetermined period, comprising a first signal generating step of inverting a signal level of the transmission signal in synchronization with a rising edge of the clock after the input of the pulse signal; a second signal generating step of inverting a signal level of the transmission signal in synchronization with the input of the pulse signal; and an output selecting step of selecting an output at the first signal generating step when the predetermined period is shorter than a period of a receiving clock and selecting an output at the second signal generating step when the first period is longer than the period of the receiving clock.

"A signal receiving method according to the present invention is a transmission method of receiving a transmission signal in synchronization with a clock having a predetermined period, comprising a first level retaining step of retaining a signal level of the transmission signal at a rising edge of the clock as well as at a falling edge of the clock; a first selecting step of selecting one of two signal levels retained at the first level retaining step; a second level retaining step of retaining an output at the first selecting step at a rising edge of the clock as well as at a falling edge of the clock; a second selecting step of selecting and outputting one of two signal levels retained at the second level retaining step; a preceding level retaining step of retaining an output at the second selecting step at a rising edge of the second clock; and an EXOR step of inputting the output at the second selecting step and an output at the preceding level retaining step to generate and output a pulse signal from an exclusive logical sum of the two outputs.

"According to a transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method of the present invention, when sending and receiving apparatuses having different operation clock frequencies send/receive a control signal, a problem of metastability can be solved and a delay of the control signal can be suppressed."

URL and more information on this patent, see: Uehara, Teruaki. Transmission and Receiving Apparatus and Method Having Different Sending and Receiving Clocks. U.S. Patent Number 8804887, filed October 5, 2010, and published online on August 12, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8804887.PN.&OS=PN/8804887RS=PN/8804887

Keywords for this news article include: Electronics, LAPIS Semiconductor Co. Ltd..

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Source: Electronics Newsweekly


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