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Patent Issued for Three-Dimensional Semiconductor Memory Devices Using Direct Strapping Line Connections

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Lee, Bongyong (Suwon-si, KR); Kim, Sang-Hoon (Giheung-gu, KR); Lee, Ae-Jeong (Cheongju-si, KR); Kim, Dongchan (Seoul, KR), filed on July 6, 2012, was published online on August 12, 2014.

The patent's assignee for patent number 8803222 is Samsung Electronics Co., Ltd. (KR).

News editors obtained the following quote from the background information supplied by the inventors: "Embodiments of the subject matter relate generally to semiconductor devices and, more particularly, to three-dimensional semiconductor memory devices and methods of fabricating the same.

"Due to their small size, multifunctional capabilities and/or low cost, semiconductor devices are important elements in the electronic industry. Higher integration of semiconductor devices is desired to satisfy consumer demands for superior performance and lower cost. In the case of semiconductor memory devices, since their integration is an important factor in determining product prices, increased integration is especially desirable.

"In typical two-dimensional or planar semiconductor memory devices, the degree of integration is generally limited by the area occupied by a unit memory cell, which may be limited by fine pattern forming technology. In particular, the expense of process equipment needed to increase pattern fineness may act as a practical limitation on increasing integration for two-dimensional or planar semiconductor memory devices. To overcome such a limitation, there have been recently proposed three-dimensional semiconductor memory devices having multiple layers of memory cells."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Some embodiments of inventive subject matter provide memory devices including a plurality of elongate gate stacks extending in parallel on a substrate, at least one insulation region disposed in a trench between adjacent ones of the gate stacks, the at least one insulation region having linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

"In further embodiments, each of the gate stacks may include a plurality of vertical channel regions distributed along a first direction. The plugs may be spaced apart along the first direction. The at least one strapping line may extend along the first horizontal direction.

"The devices may further include at least one bit line electrically connected to the vertical channel regions and extending along a second direction perpendicular to the first direction. Top surfaces of the plugs may be located at a level higher than top surfaces of the vertical channel regions and lower than the at least one bit line and the at least one strapping line.

"In some embodiments, the at least one insulation region may include a plurality of insulation regions disposed between respective adjacent pairs of the gate stacks, and the at least one strapping line may include a plurality of strapping lines, respective ones of which are disposed on respective ones of the insulation regions. The devices may further include a common source line electrically connected in common to the plurality of strapping lines. The common source line may be disposed at the same level as the at least one bit line. The devices may also include a barrier layer conforming to bottom and side surfaces of the at least one insulation region.

"Further embodiments provide methods including forming a mold stack comprising alternately arranged sacrificial layers and insulating layers on a substrate. Vertical channel regions passing through the mold stack are formed. A trench is formed in the mold stack between adjacent rows of the vertical channel regions, exposing a portion of the substrate. The trench has a linear first portion of a first width and a widened second portion of a second width greater than the first width. A common source region is formed in the exposed portion of the substrate. Portions of the sacrificial layers exposed by the trench are replaced with conductive material to form a gate stack including alternately arranged insulating layers and gate electrode layers. An insulation region is formed that fills the first portion of the trench, partially fills the second portion of the trench and leaves a hole exposing a portion of the common source region. A conductive plug is formed in the hole and connected to the common source region. A strapping line is formed on and in direct electrical contact with the plug. A bit line is formed, electrically connected to at least some of the vertical channel regions.

"The methods may further include supplying impurities into an upper portion of the vertical channel to form a drain region before forming of the trench. A common source line may be formed simultaneously with forming the bit line using a common material layer.

"An interlayer dielectric may be formed on the substrate, covering the strapping line, and first and second contacts may be formed, passing through the interlayer dielectric and electrically contacting respective one of a vertical channel region and the strapping line.

"In further embodiments, methods include forming a mold stack comprising alternately arranged sacrificial layers and insulating layers on a substrate and forming rows of vertical channel regions passing through the mold stack. The methods further include forming respective trenches in the mold stack between adjacent ones of the rows of the vertical channel regions and exposing portions of the substrate, the trenches each having linear first portions of a first width and spaced-apart widened second portions having a second width greater than the first width. Common source regions are formed in the exposed portions of the substrate, and respective gate stacks are formed between respective adjacent pairs of the trenches from the mold stack. Respective insulation regions are formed in respective ones of the trenches, wherein portions of the insulation regions in the widened second portions of the trenches have holes therethrough that expose portions of the common source regions. Conductive plugs are formed in the holes and connected to the common source regions. Respective strapping lines are formed on respective ones of the insulation regions and in direct electrical contact with the plugs. A plurality of bit lines is formed, the bit lines crossing the strapping lines and electrically connected to the vertical channel regions."

For additional information on this patent, see: Lee, Bongyong; Kim, Sang-Hoon; Lee, Ae-Jeong; Kim, Dongchan. Three-Dimensional Semiconductor Memory Devices Using Direct Strapping Line Connections. U.S. Patent Number 8803222, filed July 6, 2012, and published online on August 12, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8803222.PN.&OS=PN/8803222RS=PN/8803222

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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