News Column

Patent Issued for Test Element Group and Semiconductor Device

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Bairo, Masaaki (Kanagawa, JP), filed on March 25, 2011, was published online on August 12, 2014.

The assignee for this patent, patent number 8805637, is Sony Corporation (Tokyo, JP).

Reporters obtained the following quote from the background information supplied by the inventors: "This invention relates to a test element group (TEG) including a large number of elements connected to each other and a semiconductor device which includes a test element group provided on a semiconductor substrate.

"In recent years, together with refinement of elements, the layout dependency of element characteristics has become notable. In addition, a dispersion in element characteristic within a wafer has increased. Such layout dependency and dispersion have become a subject upon circuit fabrication. For example, the layout dependency of a threshold voltage, a current-voltage characteristic and so forth and the wafer in-plane dispersion of MOSFETs have a significant influence on the reliability of semiconductor devices and the yield upon fabrication.

"As a method of improving the reliability of semiconductor devices and the yield upon fabrication of semiconductor devices, circuit designing is generally used wherein the layout dependency of an element characteristic and the dispersion in element characteristic on a fabrication line are grasped and permitted. Further, to monitor the layout dependency in element characteristic and the characteristic dispersion on a fabrication line of semiconductor devices and manage the numerical values of them leads to stabilization of the yield of semiconductor devices.

"In the past, as a method of measuring the layout dependency of an element characteristic and the dispersion of an element characteristic, a method of evaluating a characteristic of a unit element included in each of a plurality of TEGs provided on a wafer is known. Since the TEG includes an element similar to an actual operation element used in a semiconductor element, by evaluating the TEG, the layout dependency of a characteristic and the characteristic dispersion of actual operation elements in the semiconductor device can be estimated. However, every time the generation advances, the layout is complicated and the amount of data of element characteristics necessary for circuit design increases, and also the number of elements whose evaluation is required increases.

"Therefore, in an existing evaluation method where a plurality of TEGs in each of which one or several elements which can be evaluated are incorporated, the area for incorporating a required number of TEGs in a semiconductor chip becomes very great. Therefore, in recent years, a method has been proposed wherein, as seen in FIG. 12, a large number of elements such as D(1, 1), D(1, 2), . . . , D(1, n), D(2, 1), D(2, 2), . . . , D(2, n), . . . are disposed in a matrix to achieve a high installation density of elements and a characteristic of the large number of elements is acquired over a small TEG area. The method is disclosed, in Japanese Patent Laid-Open No. 2007-103946 (hereinafter referred to as Patent Document 1)."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "The present disclosure provides one or more inventions to address the foregoing problems and to facilitate element testing with minimized signal line usage.

"One embodiment that is consistent with the present invention includes, a device comprising a plurality of elements separated into groups, each element including an activation terminal, an input terminal and an output terminal, a plurality of first signal lines, and a plurality of second signal lines, where the input terminals of each element in each group are commonly connected to one of the plurality of first signal lines, the input terminals of the different groups are connected to different first signal lines, and the output terminals of the each element in each group are independently connected to a different one of the plurality of second signal lines.

"In another embodiment consistent with the present invention, the output terminals of elements in different groups share a common second signal line.

"In another embodiment consistent with the present invention, the output terminal of at least one element in one group is independently connected to a first signal line of another group.

"In another embodiment consistent with the present invention, the device includes a selection circuit that includes a plurality of selection elements, each selection element electrically coupled to the activation terminal of a corresponding element.

"In another embodiment consistent with the present invention, each selection element sends a selection signal to the activation terminal of the corresponding element when the element is selected by the selection circuit.

"In another embodiment consistent with the present invention, the device includes a selection circuit that selects one element from each group, each selected element not sharing a common second signal line, where each selected element receives a current signal from the first signal line and outputs the current signal to the second signal line connected to the selected element.

"In another embodiment consistent with the present invention, the current sent through the first signal line is not output from the output terminals of the non selected elements sharing the same first signal line.

"In another embodiment consistent with the present invention, the selection circuit simultaneously selects one element from each group with the selected elements not sharing a common second signal line.

"In another embodiment consistent with the present invention, each element is a pixel cell.

"One embodiment consistent with the present invention includes a method of testing a plurality of elements of device arranged into groups with each element including an activation terminal, an input terminal and an output terminal, the device also including a plurality of first signal lines and a plurality of second signal lines, the input terminals of each element in each group being commonly connected to one of the plurality of first signal lines, the input terminals of the different groups being connected to different first signal lines, and the output terminals of the each element in each group being independently connected to a different one of the plurality of second signal lines, the method comprising the steps of activating one of the plurality of elements by sending a first signal to the activation terminal of the element, sending a second signal to the input terminal of the activated element by the first signal line, and measuring a characteristic of the activated element by evaluating a third signal on the second signal line connected to the activated element.

"In another embodiment consistent with the present invention, the third signal is sent on a second signal line connected to at least one element in another group.

"In another embodiment consistent with the present invention, the third signal is sent on a first signal line connected to at least one element in another group.

"In another embodiment consistent with the present invention, a selection circuit sends the first signal to each selected element.

"In another embodiment consistent with the present invention, the selection circuit includes a plurality of selection elements, each selection element being electrically connected to the activation terminal of a corresponding element.

"In another embodiment consistent with the present invention, each selected element does not share a common second signal line, and the second signal is a current signal sent to the input terminal of each selected element by the first signal line and is output from the output terminal of the selected element to the second signal line connected to the selected element.

"In another embodiment consistent with the present invention, the second signal sent on the first signal line is not output from the output terminals of the non selected elements sharing the same first signal line.

"In another embodiment consistent with the present invention the method includes the step of simultaneously activating one element in each group by sending the first signal to each selected element in each group, where the selected elements do not share a common second signal line.

"In another embodiment consistent with the present invention, each element is a pixel cell.

"One embodiment that is consistent with the present invention includes a device comprising a plurality of elements, each element including an activation terminal, an input terminal and an output terminal, a plurality of first signal lines, and a plurality of second signal lines, where the input terminals of each element are commonly connected to one of the plurality of first signal lines, and the output terminals of the each element are independently connected to a different one of the plurality of second signal lines.

"One embodiment consistent with the present invention includes a method of testing a plurality of elements of a device, each element including an activation terminal, an input terminal and an output terminal, the device also including a first signal line and a plurality of second signal lines, the input terminal of each element being commonly connected to the first signal line, and the output terminal of each element being independently connected to a different second signal line, the method comprising activating one of the plurality of elements by sending a first signal to the activation terminal of the element, sending a second signal to the input terminal of the activated element by the first signal line connected thereto, and measuring a characteristic of the activated element by evaluating a third signal on the second signal line connected to the activated element.

"Other systems, methods, features, and advantages of the present invention(s) will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims."

For more information, see this patent: Bairo, Masaaki. Test Element Group and Semiconductor Device. U.S. Patent Number 8805637, filed March 25, 2011, and published online on August 12, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8805637.PN.&OS=PN/8805637RS=PN/8805637

Keywords for this news article include: Electronics, Semiconductor, Sony Corporation.

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Source: Electronics Newsweekly


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