The assignee for this patent, patent number 8802563, is
Reporters obtained the following quote from the background information supplied by the inventors: "Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
"Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as 'crosstalk') are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
"In semiconductor interconnect structures, electromigration (EM) has been identified as one metal failure mechanism. Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size decreases, the practical significance of EM increases.
"EM is one of the worst reliability concerns for very large scale integrated (VLSI) circuits and manufacturing since the 1960's. The problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip. Voids are created inside the metal conductors of an interconnect structure due to metal ion movement caused by the high density of current flow.
"Although the fast diffusion path in metal interconnects varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that metal atoms, such as Cu atoms, transported along the metal/post planarized dielectric cap interface play an important role on the EM lifetime projection. The EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction to the bottom of the interconnect, which eventually results in a circuit dead opening.
"In view of the above, there is a need for providing interconnect structures having enhanced EM resistance."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The present invention provides semiconductor interconnect structures that have improved EM reliability. The present invention further provides semiconductor interconnect structures that include a surface-repair material that fills any hollow-metal related defects located within a conductive material of the inventive interconnect structure. As such, the inventive interconnect structures exhibit a decreased in in-line defect related yield loss. The present invention further provides interconnect structures that have better reliability and technology extendibility for the semiconductor industry.
"In general terms, the present invention provides an interconnect structure including: a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material having an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects located therein; and a surface repair material located within and filling the hollow-metal related defects that are present at the upper surface of the at least one conductive material.
"The surface repair material, which is embedded within the conductive material, includes any noble metal or noble metal alloy that is resistant to corrosion or oxidation. Preferably, the surface repair material includes one of Ru, Ir, Rh, Pt, Co, W and alloys thereof such as, for example, Co(W,P,B). It is observed that the surface repair material may comprise the same or different, preferably the same, noble metal material as an optional noble metal cap to be subsequently formed. When the same materials are used for the surface repair material and the noble metal cap there is no interface formed between these same materials. As such, the surface repair material and the noble metal cap could be considered as a single component of the interconnect structure which has unitary construction. When two different materials are used for the surface repair material and the noble metal cap, an interface exists between the surface repair material and the noble metal cap. As such, the surface repair material and the noble metal cap are separate and distinct components that are present in the inventive interconnect structure. Similarly, when a dielectric material is used as a capping layer directly on the interconnect structure and the embedded repair metal material surface, an interface exists between the surface repair material and the dielectric capping layer.
"The dielectric material which is present in the inventive interconnect structure may be any interconnect dielectric material having a dielectric constant of about 4.0 or less.
"Illustratively, the dielectric material employed in the present invention comprises silicon dioxide, a silsesquioxane, a C doped oxide (i.e., an organosilicate) that includes at least atoms of Si, C, O and H, a thermosetting polyarylene ether, or multilayers thereof. The dielectric material may be porous, non-porous or contain regions and/or surfaces that are porous and other regions and/or surfaces that are non-porous.
"The conductive material which forms an embedded conductive region within the interconnect structure includes any material that has the ability to transfer electricity. Examples of conductive material that can be present in the conductive region include, for example, polySi, a conductive metal, a conductive metal alloy, a conductive metal silicide or combinations and multilayers thereof. In one embodiment of the present invention, the conductive material includes a conductive metal such as, for example, Cu, W, and/or Al. In a highly preferred embodiment of the present invention, the conductive material includes a Cu-containing conductive material such as, for example, Cu, or a Cu alloy (such as AlCu).
"The inventive structure further includes a U-shaped diffusion barrier that separates the conductive material from the dielectric material. The diffusion barrier prevents diffusion of the conductive material into the dielectric material. Examples of diffusion barriers that can be present within the conductive region include, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, IrTa, IrTaN, W, WN or combinations and multilayers thereof.
"The conductive material may be present within a via opening, a line opening, a combined via and line opening or any combination thereof.
"In some embodiments of the present invention, a dielectric capping layer is located above the inventive structure.
"In yet other embodiments of the present invention, a noble metal cap is located on the surface of the at least one conductive material. When present, the noble metal cap does not extend onto the dielectric material. Preferably, the noble metal cap does not extend onto an upper surface of a U-shaped diffusion barrier that is present between the at least one conductive material and the dielectric material.
"The term 'noble metal' when referring to the cap located atop the at least one conductive material includes any metal that is resistant to corrosion or oxidation. The preferred noble metals that can be used in the present invention are selected from the group consisting of Ru, Ir, Rh, Pt, Co, W and alloys thereof. More preferably, the noble metal employed as the noble metal cap comprises Ru or a Ru alloy. In a preferred embodiment, the noble metal cap is self aligned to the underlying conductive material that is embedded within the dielectric material. That is, the noble metal cap preferably does not extend beyond the upper surface of the conductive material. In yet another embodiment, the noble metal cap extends onto an upper surface of a U-shaped diffusion barrier that separates the conductive material from the dielectric material. In no instance does the noble metal cap or residues thereof extend onto the dielectric material.
"When a noble metal cap is present, the inventive interconnect structure also typically includes a dielectric capping layer.
"In addition to the interconnect structures mentioned above, the present invention also provides a method of fabricating the same. In general terms, the inventive method includes: providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and
"filling said hollow-metal related defects with a surface repair material."
For more information, see this patent: Yang, Chih-Chao; Murray, Conal E.. Surface Repair Structure and Process for Interconnect Applications. U.S. Patent Number 8802563, filed
Keywords for this news article include: Electronics, Semiconductor,
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OCTOBER 30, 2014
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