Patent number 8803324 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates generally to semiconductor devices and methods of manufacturing the same, and in particular to semiconductor devices including contact plugs and lines and methods of manufacturing the same.
"An overlay margin between a metal line and a contact plug becomes smaller as cell area decreases. This decrease in cell area is directly attributable to the increase in the degree of integration of memory devices. As the overlay margin becomes smaller, there is a high probability that metal lines and contact plugs may be misaligned because the metal lines are formed after forming the contact plugs.
"If metal lines and contact plugs are misaligned as described above, the distance between a contact plug and a metal line adjacent to the contact plug decreases. The distance between the contact plug and the adjacent metal line may become smaller than the critical distance at which leakage current does not occur between adjacent conductive layers. As a result, a leakage current may be generated between the contact plug and the adjacent metal line.
"Furthermore, unwanted capacitance between metal lines increases as the distance between adjacent metal lines decreases."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "A semiconductor device suitable for preventing a leakage current from occurring between a contact plug and a line adjacent to the contact plug, and a method of manufacturing the same, are discussed below in accordance with an embodiment of the present invention.
"In an embodiment, a semiconductor device includes a first interlayer insulating layer, an etch stop layer formed on the first interlayer insulating layer, contact holes formed to penetrate the etch stop layer and the first interlayer insulating layer, contact plugs formed within the respective contact holes and configured to have a top surface lower than a top surface of the etch stop layer, a second interlayer insulating layer formed over the contact plugs and the etch stop layer, line trenches formed to penetrate the second interlayer insulating layer, wherein the respective contact plugs are exposed in the line trenches, and lines formed within the trenches and coupled to the respective contact plugs.
"In accordance with another embodiment, a method of manufacturing a semiconductor device includes forming contact plugs, each having a top surface having a lower height than a top surface of an etch stop layer, within respective contact holes formed to penetrate a first interlayer insulating layer and the etch stop layer formed on the first interlayer insulating layer; forming a second interlayer insulating layer on the results in which the contact plugs are formed; forming line trenches through which the respective contact plugs are exposed by etching the second interlayer insulating layer; and forming lines, coupled to the contact plugs, within the respective line trenches."
URL and more information on this patent, see: Lee, Young Jin. Semiconductor Devices and Methods of Manufacturing the Same. U.S. Patent Number 8803324, filed
Keywords for this news article include: Electronics,
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OCTOBER 31, 2014
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