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Patent Issued for Semiconductor Device Including Test Circuit and Burn-In Test Method

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Cho, Jin Hee (Cheongju-si, KR), filed on April 23, 2012, was published online on August 12, 2014.

The patent's assignee for patent number 8804444 is SK Hynix Inc. (Gyeonggi-do, KR).

News editors obtained the following quote from the background information supplied by the inventors: "In general, in a semiconductor device, to improve reliability a burn-in test is performed to remove memory cells with an initial fail probability. The burn-in test involves a test in which a factor exerting a substantial influence on determining failure of a semiconductor device, for example, a voltage is applied to memory cells by raising the voltage to a higher than normal state to induce a stress in the semiconductor device, so as to determine whether or not a fail has occurred in the semiconductor device.

"FIG. 1 is a block diagram showing the configuration of a conventional semiconductor device for performing a burn-in test.

"Referring to FIG. 1, the conventional semiconductor device includes a data input/output circuit 11 and a test circuit 12. The data input/output circuit 11 is configured to apply an internal command ICMD and first to fourth internal addresses IA to the test circuit 12 and receive first to fourth test mode signals TM. The data input/output circuit 11 is reset or performs a burn-in test in response to the first to fourth test mode signals TM. The test circuit 12 is configured to decode the first to fourth internal addresses IA in a state in which the preset internal command ICMD is inputted and generate the first to fourth test mode signals TM.

"Burn-in test operations performed in the semiconductor device configured in this way will be described with reference to FIG. 2.

"First, the test circuit 12 decodes the first to fourth internal addresses IA in the state in which the preset internal command ICMD is inputted and generates the first to fourth test mode signals TM which are selectively enabled. In detail, the test circuit 12 enables the first test mode signal TM to a logic high level when all the first to fourth internal addresses IA have logic low levels, and the test circuit 12 enables the second test mode signal TM to a logic high level when only the fourth internal address IA has a logic high level. Also, the test circuit 12 enables the third test mode signal TM to a logic high level when the second internal address IA and the fourth internal address IA have logic high levels, and the test circuit 12 enables the fourth test mode signal TM to a logic high level when the third and fourth internal addresses IA have logic high levels.

"Next, the data input/output circuit 11 is reset or performs a burn-in test in response to the first to fourth test mode signals TM. That is to say, the data input/output circuit 11 is reset when the first test mode signal TM is enabled, and performs the burn-in test when one of the second to fourth test mode signals TM is enabled. In detail, a stress voltage is applied to the memory cells which are connected to odd-numbered word lines of the data input/output circuit 11 when the second test mode signal TM is enabled, a stress voltage is applied to the memory cells which are connected to even-numbered word lines when the third test mode signal TM is enabled, and a stress voltage is applied to the memory cells which are connected to all word lines when the fourth test mode signal TM is enabled.

"In the semiconductor device configured as described above, the burn-in test is performed in such a manner that, after controlling word lines to be enabled, by selectively enabling the first to fourth test mode signals TM according to level combinations of the first to fourth internal addresses IA, a stress voltage is applied to memory cells connected to enabled word lines.

"While such a burn-in test is mainly performed in a wafer state, since it is not accompanied by a read operation, whether a fail has occurred in the memory cells applied with the stress voltage is not checked during the burn-in test operations. Therefore, in the conventional semiconductor device, a burn-in test is accompanied by a read operation that is additionally performed in a package state to determine if a fail has occurred in the memory cells."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Embodiments of the present invention relate to a semiconductor device including a test circuit capable of performing a burn-in test accompanied by a read operation, and a burn-in test method.

"In one embodiment, a semiconductor device includes: a test circuit configured to generate a buffer control signal in response to input data inputted through a data pad, decode test commands inputted in response to the buffer control signal, and generate test mode signals and a counting enable signal for counting row addresses and column addresses; and a data input/output circuit configured to buffer external commands in response to the buffer control signal and generate the test commands, perform a burn-in test in response to the test mode signals, and perform a read operation for memory cells corresponding to the row addresses and the column addresses.

"In another embodiment, a test circuit includes: a buffer control signal generation unit configured to generate a buffer control signal in response to input data inputted through a data pad when a burn-in test is performed in an idle state; a test command decoder configured to decode inputted test commands in response to the buffer control signal and generate test mode signals and a counting enable signal; and an address counter configured to count row addresses and column addresses in response to the counting enable signal.

"In another embodiment, a burn-in test method includes: buffering external commands and outputting test commands, when a semiconductor device is in an idle state and input data inputted through a data pad has a first level; decoding the test commands and generating test mode signals and a counting enable signal; and counting row addresses and column addresses when the counting enable signal is enabled."

For additional information on this patent, see: Cho, Jin Hee. Semiconductor Device Including Test Circuit and Burn-In Test Method. U.S. Patent Number 8804444, filed April 23, 2012, and published online on August 12, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8804444.PN.&OS=PN/8804444RS=PN/8804444

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

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Source: Electronics Newsweekly


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