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Patent Issued for Semiconductor Device Based on Power Gating in Multilevel Wiring Structure

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- PS4 Luxco S.A.R.L. (Luxembourg, LU) has been issued patent number 8806411, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Ishii, Toshinao (Tokyo, JP).

This patent was filed on June 28, 2013 and was published online on August 12, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Japanese Patent Kokai Publication No. JP2009-170650A describes arrangement of circuit cells and power supply lines of a semiconductor device using an MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technique (hereinafter referred to as 'power gating'). Further discussion of the power gating can be found in commonly assigned, U.S. Pat. No. 5,486,774, U.S. Pat. No. 6,034,563 and U.S. Pat. No. 6,215,159.

"The entire disclosures of the above mentioned Patent Documents are incorporated herein by reference thereto. The following analyses are made by the present invention.

"As illustrated in FIG. 3 of the above Patent Document, based on the semiconductor device disclosed in the Patent Document, at least a total of three power supply lines of branch lines 20D and 20S and a virtual VSS line 30S need to be arranged in a single cell array (cell line). In addition, while not explicitly illustrated in FIG. 3 of the above Patent Document, normally, a signal array is arranged in a region between the branch line 20D and the virtual VSS line VSSV.

"Thus, the regions that can be occupied by the power supply lines in the height direction of the cell array (in the direction perpendicular to the direction in which the cell array extends) are limited. Therefore, based on this configuration, for example, if miniaturization of circuit elements is advanced and if the size of the cell array in the height direction thereof is reduced, the regions that can be occupied by the power supply lines are accordingly reduced. As a result, resistance of the power supply lines is increased, counted as a problem."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "In one embodiment, there is provided a semiconductor device, comprising:

"a first circuit cell array extending in a first direction;

"a second circuit cell array extending in the first direction substantially in parallel to the first circuit cell array;

"first and second power supply lines each extending in the first direction and arranged over the first circuit cell array, the first power supply line being supplied with a first power source voltage;

"a third power supply line extending in the first direction separately from the second power supply line, arranged over the second circuit cell array, and supplied with a second power source voltage;

"a first transistor coupled between the second power supply line and the third power supply line; and

"a first circuit arranged on the first circuit cell array and operating on the first power source voltage supplied from the first power supply line and the second power source voltage supplied from the second power supply line.

"In another embodiment, there is provided a semiconductor device, comprising:

"a first circuit cell array extending in a first direction;

"a second circuit cell array extending in the first direction substantially in parallel to the first circuit cell array;

"a main power supply line elongated in the first direction and arranged over the first circuit cell array;

"a pseudo power supply line elongated in parallel to and separately from the first main supply line and arranged over the second circuit cell array;

"a first circuit disposed in the first circuit cell array and including a first power supply node that is coupled to the main power supply line;

"a second circuit disposed in the second circuit cell array and including a second power supply node that is coupled to the pseudo power supply line; and

"a transistor coupled between the main power supply line and the pseudo power supply line."

For the URL and additional information on this patent, see: Ishii, Toshinao. Semiconductor Device Based on Power Gating in Multilevel Wiring Structure. U.S. Patent Number 8806411, filed June 28, 2013, and published online on August 12, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8806411.PN.&OS=PN/8806411RS=PN/8806411

Keywords for this news article include: Electronics, Semiconductor, PS4 Luxco S.A.R.L..

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Source: Electronics Newsweekly


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