News Column

Patent Issued for Rule Coverage Rate Auto-Extraction and Rule Number Auto-Mark

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu, TW) has been issued patent number 8806417, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Chao, Chih-Ming (Hsinchu, TW); Ting, Jyh-Kang (Baoshan Township, TW); Chen, Chin-An (Zhudong Township, TW); Wu, Pei-tzu (Hsinchu, TW); Lee, Chun-Yi (Beipu Township, TW).

This patent was filed on April 26, 2013 and was published online on August 12, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "In semiconductor manufacturing, a semiconductor wafer often undergoes many processing steps or stages before a completed die is formed. For example, lithographic processes are performed on the semiconductor wafer using a mask and photoresist to transfer a particular design or layout onto the wafer. Design Rules (DRs) are a series of parameters provided by semiconductor manufacturers that enable a designer to verify the correctness of a mask or mask set. Design rules are often specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to, among other things, ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the resultant components work as designed.

"Conventional basic design rules 10 are illustrated in FIG. 1 for single-layer rules. A width rule 12 specifies the minimum width of any shape or object 14 in the design. A spacing rule 16 specifies the minimum distance between two adjacent shapes or objects 14. Such rules typically exist for each layer formed in the semiconductor manufacturing process, with the lowest layers having the smallest rules, and the highest metal layers having larger rules.

"A two-layer rule specifies a relationship that should exist between two layers. For example, an enclosure rule 18 can specify that an object 20 of one type, such as a contact or via, must be covered, with some additional margin, by a metal layer 22. Other design rules, such as minimum area rules are also utilized. Minimum area rules designate a minimum area to be masked or formed, while antenna rules are more complex rules that check ratios of areas of multiple layers of a net for configurations that can result in problems when intermediate layers are etched. Various other design rules can also be provided by the semiconductor manufacturer.

"Design Rule Checking (DRC) further determines whether the physical layout of a particular chip layout satisfies a series of Design Rules. Design rule checking is a major step during physical verification signoff on the design, and can also involve a Layout Versus Schematic (LVS) check, XOR Checks, Electrical Rule Check (ERC) and Antenna Checks. For advanced processes some fabs also insist upon the use of more restricted rules to improve yield.

"Over time, device sizes are becoming smaller and smaller, and design rule sets have become increasingly more complex with each subsequent generation of semiconductor process. As such, extensive periods of time are spent design rule checking and manually examining statistics associated with the design rules and DRCs."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "The following presents an overview of the disclosure in order to provide a basic understanding of one or more aspects of the disclosure. This is not an extensive overview of the disclosure, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

"According to various embodiments, the present disclosure relates to a method for analyzing an integrated circuit layout. The method comprises providing a target integrated circuit layout having a plurality of design rules associated therewith. The plurality of design rules, for example, comprise minimum rules and standard rules used in the target integrated circuit layout. The minimum rules, for example, are associated with smallest limitations of the respective design rules, and the standard rules are associated with limitations that are greater than the respective minimum rules.

"A first design rule check is performed on the target integrated circuit layout, wherein a first set of violations of the plurality of design rules and each design rule respectively associated with the first set of violations are recorded. According to other examples, a second design rule check, such as a reverse design rule check, is performed on the target integrated circuit layout, wherein a second set of violations of the plurality of design rules and each design rule respectively associated with the second set violations are recorded.

"An analysis of the first set of violations, second set of violations, each design rule respectively associated with the first set of violations and second set of violations, and a frequency of usage of each of the plurality of design rules is further performed, wherein a rule usage rate is determined based on the analysis. The rule usage rate, for example, comprises an overall number of minimum rules used throughout the target integrated circuit layout. In another example, the rule usage rate further comprises a number of violations of each design rule respectively associated with the first set of violations and second set of violations.

"A rule database is further compiled or otherwise formed, wherein statistics associated with the rule usage rate are defined and utilized in subsequent implementation of the target integrated circuit layout. Forming the rule database, for example, may comprise forming a searchable database of the rule usage rate and one or more of the first set of violations, second set of violations, each design rule respectively associated with the first set of violations and second set of violations, and the frequency of usage of each of the plurality of design rules. Further, a value associated with each design rule respectively associated with the first set of violations and second set violations of the plurality of design rules can be recorded and further implemented in the rule database. The value, for example, comprises a measurement of a feature associated with the respective design rule.

"In accordance with various examples, the rule usage rate can be further mapped across the target integrated circuit layout. Mapping the rule usage rate across the target integrated circuit layout, for example, can further comprises marking rules as acceptable or unacceptable based on one or more of the analysis and an operator intervention.

"One or more of the one or more of the minimum rules and/or design rules respectively associated with the first set of violations and second set of violations can be replaced with a standard rule based, at least in part, on the rule usage rate, therein defining a modified integrated circuit layout. Such replacement with a standard rule generally improves a pass/fail yield rate associated with the target integrated circuit layout.

"One or more of performing the first design rule check, second design rule check, analysis, determination of the rule usage rate, and forming the rule database can be repeated in an iterative manner after substituting the target integrated circuit layout with the modified integrated circuit layout.

"A photolithography mask can be further generated based on the modified integrated circuit layout, wherein a number minimum design rules utilized in the mask is advantageously minimized."

For the URL and additional information on this patent, see: Chao, Chih-Ming; Ting, Jyh-Kang; Chen, Chin-An; Wu, Pei-tzu; Lee, Chun-Yi. Rule Coverage Rate Auto-Extraction and Rule Number Auto-Mark. U.S. Patent Number 8806417, filed April 26, 2013, and published online on August 12, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8806417.PN.&OS=PN/8806417RS=PN/8806417

Keywords for this news article include: Electronics, Taiwan Semiconductor Manufacturing Co. Ltd.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters