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Patent Issued for Methods of Operating Semiconductor Device

August 27, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Aritome, Seiichi (Seongnam, KR), filed on July 5, 2012, was published online on August 12, 2014.

The assignee for this patent, patent number 8804426, is SK Hynix Inc. (Gyeonggi-do, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "Embodiments of this invention relate generally to methods of operating a semiconductor device and, more particularly to program methods of a semiconductor device.

"A semiconductor device includes a memory cell array in which data is stored. The memory cell array includes a plurality of cell blocks. Each of the cell blocks includes a plurality of cell strings. The cell strings have the same structure, and only one of the cell strings is described below in detail.

"FIG. 1 is a sectional view of a cell string for illustrating known phenomenon.

"Referring to FIG. 1, the cell string includes a plurality of memory cells and switching elements which are formed over a semiconductor substrate 10. The switching elements comprise a drain select transistor and a source select transistor. In case of a NAND flash memory device, the plurality of memory cells is formed, for example, between the drain select transistor and the source select transistor, and a junction 11 is formed in the semiconductor substrate 10 between the transistors and the respective memory cells. Each of the drain and source select transistors includes a gate insulating layer 12 and a gate electrode 14 which are sequentially stacked over the semiconductor substrate 10. Each of the memory cells includes the gate insulating layer 12, a floating gate 16, a dielectric layer 17, and a control gate 18 which are sequentially stacked over the semiconductor substrate 10. The gate insulating layer 12 is made of an insulating material, such as an oxide layer. The dielectric layer 17 may have a stack structure including an oxide layer, a nitride layer, and an oxide layer, or it may be made of a high-k material. The floating gate 16, the control gate 18, and the gate electrode 14 are made of a conductive material, such as polysilicon. The drain select transistors included in different cell strings are coupled to a drain select line DSL, the source select transistors included in different cell strings are coupled to a source select line SSL, and the memory cells included in different cell strings are coupled to respective word lines WLn-k to WLn+k.

"A method of programming a semiconductor memory device including the cell string is described below.

"Referring to FIGS. 1 and 2, a program permission voltage (for example, a ground voltage) is applied to the channel of a selected cell string (it is hereinafter assumed that the cell string of FIG. 1 has been selected), a program voltage Vpgm is applied to a selected word line (for example, WLn) coupled to a selected memory cell, and a pass voltage Vpass is applied to the remaining unselected word lines WLn-k to WLn-1 and WLn+1 to WLn+k. When the program voltage Vpgm is applied to the selected word line WLn, the potential of the floating gate 16 rises owing to coupling between the control gate 18 and the floating gate 16. As a result, electrons within the semiconductor substrate 10 are introduced into the floating gate 16 through the gate insulating layer 12 because of a tunneling phenomenon. An operation in which the electrons are introduced into the floating gate 16 is called a program operation. In contrast, an operation in which electrons in the floating date 16, for example, electrons introduced into the floating gate 16 are drained out to the semiconductor substrate 10 is called an erase operation.

"Recently, a multi-level cell (MLC) method of programming one memory cell in various levels is chiefly used. In order to program one memory cell in various levels, the distribution widths of the threshold voltages of memory cells must be narrow. To this end, a program operation using an Incremental Step Pulse Program (hereinafter referred to as an `ISPP`) method is used.

"A program operation using an ISPP method is performed by applying the program voltage Vpgm to the selected word line WLn and applying the pass voltage Vpass to the remaining unselected word lines WLn-k to WLn-1 and WLn+1 to WLn+k. In general, the pass voltage Vpass has a level lower than the program voltage Vpgm. More particularly, the program voltage Vpgm having a low level is applied at the early stage of program, and the program voltage Vpgm is raised by a step voltage. After the program voltage Vpgm and the pass voltage Vpass are applied, a verify operation for determining whether the threshold voltage of the selected memory cell has reached a target voltage is performed. If, as a result of the verify operation, the threshold voltage of the selected memory cell is determined not to have reached the target voltage, the program operation and the verify operation are repeated by applying the program voltage Vpgm and the pass voltage Vpass while gradually raising the program voltage Vpgm by the step voltage until the threshold voltage of the selected memory cell reaches the target voltage. If, as a result of the verify operation, the threshold voltage of the selected memory cell is determined to have reached the target voltage, the program operation is terminated.

"While the program operation is performed, the program voltage Vpgm gradually rises, whereas the pass voltage Vpass(1) having a constant level is applied to the remaining unselected word lines WLn-k to WLn-1 and WLn+1 to WLn+k. Accordingly, a difference between the program voltage Vpgm and the pass voltage Vpass gradually increases. Furthermore, while the program operation is performed, whereas an increasing pass voltage Vpass(2) is applied to the remaining unselected word lines WLn-k to WLn-1 and WLn+1 to WLn+k. The increasing pass voltage Vpass(2) increases as a step-up level lower than that of the program voltage Vpgm. In case of unselected memory cells adjacent to the selected memory cell, if the program voltage Vpgm applied to the selected word line WLn becomes higher than a specific level, the unselected memory cells may be erased under the influence of the raised program voltage Vpgm of the adjacent selected memory cell. That is, if the program voltage Vpgm gradually rises and then voltage difference between the program voltage Vpgm and the pass voltage Vpass reaches a Critical voltage Difference (hereinafter referred to as a `CD`), a breakdown BD between the unselected memory cells and the selected memory cells may be occurred. Furthermore, electrons which are stored in the floating gate 16 of the unselected memory cells adjacent to the selected memory cell may be ejected to the control gate 18 of the selected memory cell, and so the threshold voltages of the unselected memory cells may be decreased

"As described above, when the program voltage Vpgm applied to the selected word line WLn in the program operation gradually rises and thus a difference between the program voltage Vpgm and the pass voltage Vpgm reaches the CD, the threshold voltages of unselected memory cells adjacent to the selected memory cell may be shifted, and the reliability of the program operation may deteriorate."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "In accordance with an exemplary embodiment of this invention, a difference between a program voltage and a pass voltage is prevented from rising higher than a critical voltage difference (CD) in a program operation in order to prevent unselected memory cells adjacent to a selected memory cell from being erased.

"Furthermore, a program voltage, which has gradually risen, remains constant after reaching a specific level in order to prevent leakage that may occur in a selected memory cell.

"A method of operating a semiconductor device according to an embodiment of the present invention includes programming selected memory cells by applying a first program voltage, which gradually rises, to a selected word line and applying a first pass voltage, which is constant, to remaining unselected word lines; and programming the selected memory cells while applying a second program voltage, which is constant, to the selected word line and applying a second pass voltage, which gradually rises, to first unselected word lines adjacent to the selected word line, when a difference between the first program voltage and the first pass voltage reaches a critical voltage difference.

"The method further includes programming the selected memory cells while applying a third pass voltage, having a lower potential than the first pass voltage by the critical voltage difference, to second unselected word lines adjacent to the first unselected word lines, respectively, when applying the second pass voltage to the first unselected word lines.

"The third pass voltage gradually rises in proportion to the second pass voltage.

"The method further includes applying a fourth pass voltage, which gradually drops, to second unselected word lines adjacent to the first unselected word lines, respectively, when applying the second pass voltage to the first unselected word lines; and applying a fifth pass voltage, gradually rising in proportion to the second pass voltage, to the second unselected word lines, when a difference between the fourth pass voltage and the second pass voltage reaches the critical voltage difference.

"The method further includes applying a sixth pass voltage, which gradually drops, to third unselected word lines adjacent to the second unselected word lines, respectively, when applying the fifth pass voltage to the second unselected word lines; and applying a seventh pass voltage which is constant to the second unselected word lines, when a difference between the sixth pass voltage and the first pass voltage reaches the critical voltage difference.

"The method further includes applying a fourth pass voltage which gradually drops to second and third unselected word lines sequentially adjacent to the first unselected word lines, when applying the second pass voltage to the first unselected word lines; and applying a fifth pass voltage, gradually rising in proportion to the second pass voltage, to the second unselected word lines, and continuing to apply the fourth pass voltage to the third unselected word lines until a difference between the first pass voltage and the fourth pass voltage reaches the critical voltage difference, when a difference between the fourth pass voltage and the second pass voltage reaches the critical voltage difference.

"The method further includes applying an eighth pass voltage, which is constant, to the second unselected word lines, when a difference between the first pass voltage and the fourth pass voltage applied to the third unselected word lines reaches the critical voltage difference.

"A method of operating a semiconductor device according to an embodiment of the present invention includes programming selected memory cells coupled to a selected word line by applying a first program voltage, gradually rising by a first step voltage, to the selected word line and by applying a ninth pass voltage, gradually rising by a lower level than the first program voltage, to remaining unselected word lines; and programming the selected memory cells while applying a second program voltage, which is constant, to the selected word line and applying a second pass voltage, gradually rising by the first step voltage, to first unselected word lines adjacent to the selected word line, when a difference between the first program voltage and the ninth pass voltage reaches a critical voltage difference while programming the selected memory cells.

"The method further includes applying a third pass voltage, having a lower potential than the ninth pass voltage by the critical voltage difference, to second unselected word lines adjacent to the first unselected word lines, respectively, when applying the second pass voltage to the first unselected word lines.

"The third pass voltage gradually rises in proportion to the second pass voltage.

"The method further includes applying a fourth pass voltage, which gradually drops, to second unselected word lines adjacent to the first unselected word lines, respectively, when applying the second pass voltage to the first unselected word lines; and applying a fifth pass voltage, gradually rising in proportion to the second pass voltage, to the second unselected word lines, when a difference between the fourth pass voltage and the second pass voltage reaches the critical voltage difference.

"The method further includes applying a sixth pass voltage, which gradually drops, to third unselected word lines adjacent to the second unselected word lines, respectively, when applying the fifth pass voltage to the second unselected word lines; and applying a tenth pass voltage, gradually rising in proportion to the ninth pass voltage, to the third unselected word lines, when a difference between the sixth pass voltage and the ninth pass voltage reaches the critical voltage difference.

"The method further includes applying a fourth pass voltage, which gradually drops, to second and third unselected word lines sequentially adjacent to the first unselected word lines, when applying the second pass voltage to the first unselected word lines; and applying a fifth pass voltage, gradually rising in proportion to the second pass voltage, to the second unselected word lines, and continuing to apply the fourth pass voltage to the third unselected word lines until a difference between the ninth pass voltage and the fourth pass voltage reaches the critical voltage difference, when a difference between the fourth pass voltage and the second pass voltage reaches the critical voltage difference.

"The method further includes applying an eleventh pass voltage, gradually rising in proportion to the ninth pass voltage, to the third unselected word lines, when a difference between the ninth pass voltage and the fourth pass voltage applied to the third unselected word lines reaches the critical voltage difference."

For more information, see this patent: Aritome, Seiichi. Methods of Operating Semiconductor Device. U.S. Patent Number 8804426, filed July 5, 2012, and published online on August 12, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8804426.PN.&OS=PN/8804426RS=PN/8804426

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

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Source: Electronics Newsweekly


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