News Column

Patent Issued for Common Mode Bias Circuit

August 27, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Rey-Losada, Daniel (San Diego, CA), filed on July 6, 2012, was published online on August 12, 2014.

The assignee for this patent, patent number 8803602, is Analog Devices, Inc. (Norwood, MA).

Reporters obtained the following quote from the background information supplied by the inventors: "It is known in the prior art that differential or pseudo-differential circuits have nodes that float at DC and prevent proper operation unless a method is provided to bias these nodes to a desired common mode. Therefore, it is known in the art to supply a DC bias voltage to a differential signal processing circuit, such as the inputs of an AC-coupled differential operational amplifier for example.

"For example, a differential amplifier 102 may be AC-coupled to the output of a transducer 101, as schematically illustrated in FIG. 1A. The transducer output may be a single-ended voltage signal, referenced to ground. To interface this signal to the differential amplifier 102, which may have an input common-mode different from the transducer output's common mode, the transducer output 101 is AC-coupled to the non-inverting input 102A of op-amp 102, while the inverting input 102B of the op-amp 102 is AC-coupled to ground, and both inputs are provided (not shown) with nominally identical DC bias voltages.

"FIG. 1B schematically illustrates a differential amplifier circuit 112 similarly configured to accept the single-ended or pseudo-differential output of transducer 101, process it, and produce a differential output signal.

"A number of biasing circuits and methods are known in the art. Two simple biasing circuits are schematically illustrated in FIG. 2A and FIG. 2B, respectively. In each case, an amplifier's inverting and non-inverting inputs are biased by coupling them to a voltage source through two biasing resistors. An alternate biasing circuit is schematically illustrated in FIG. 2C, in which an amplifier's inverting and non-inverting inputs are biased by two voltage divider circuits coupled to a voltage source. A small-signal representation 270 of such a biasing circuit is schematically illustrated in FIG. 2D."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "In a first embodiment there is provided a biasing circuit for providing bias voltage to a differential circuit configured to process signals at frequencies above a pre-determined frequency within a signal band, the differential circuit having a first signal node and a second signal node, the first signal node and second signal node together forming a differential node, the biasing circuit including a bias source having a DC voltage output, the DC voltage output producing a DC bias voltage and having: a first output impedance at DC, and a second output impedance at frequencies within the signal band; a first bias resistor having a first bias resistance, the first bias resistor coupled between the voltage output and the first signal node so as to provide a DC bias voltage to the first signal node; and a second bias resistor having a second bias resistance, the second bias resistor coupled between the voltage output and the second signal node so as to provide the DC bias voltage to the second signal node, the magnitude of the first output impedance being less than 80 percent of the smaller of the magnitude of the first bias resistance and the magnitude of the second bias resistance, and the magnitude of the second output impedance being at least 20 percent of the larger of the magnitude of the first bias resistance and the magnitude of the second bias resistance, provided that the magnitude of the first output impedance is less than fifty percent of the magnitude of the second output impedance.

"In some embodiments, the differential circuit is an amplifier. In some embodiments, the differential circuit is a buffer, a comparator, or a filter. In some embodiments, the differential circuit is an intermediate stage of an amplifier, a buffer, a comparator, or a filter. In some embodiments, the differential circuit is a pseudo-differential circuit.

"In another embodiment, a differential circuit for processing signals within a signal band above a pre-determined frequency, the differential circuit includes a differential processor having a first input and a second input, the first input and second input forming a differential input, the differential processor having a bandwidth that includes frequencies above the pre-determined frequency; a biasing amplifier having a bias non-inverting input, a feedback inverting input, and a bias output; a voltage source electrically coupled to the bias non-inverting input; a feedback path electrically coupling the feedback inverting input to the bias output, such that the biasing amplifier presents a closed-loop output impedance at DC, and a second output impedance at frequencies above the predetermined frequency; a first biasing resistance having a first terminal and a second terminal, the first terminal electrically coupled to the bias output, and the second terminal electrically coupled to the first input; a second biasing resistance having a third terminal and a fourth terminal, the third terminal electrically coupled to the bias output, and the fourth terminal electrically coupled to the second input, the magnitude of the closed-loop output impedance at DC being less than ten percent of the lower of the magnitude of the first biasing resistance and the magnitude of the second biasing resistance, and the magnitude of the second output impedance being at least two hundred percent of the higher of the magnitude of the first biasing resistance and the magnitude of the second biasing resistance.

"In some embodiments, the biasing amplifier has an open-loop output impedance of at least 1,000 ohms.

"Some embodiments also include a source of a differential signal, the differential signal having a first component output and a second component output, the first component output electrically coupled to the first input, and the second component output electrically coupled to the second input.

"Some embodiments also include a first coupling capacitor electrically coupled between the first component output and the first input, and a second coupling capacitor electrically coupled between the second component output and the second input, such that the first coupling capacitor and second coupling capacitor AC-couple the source from the differential processor.

"Some embodiments also include a source of a pseudo-differential signal having a source signal output, the source signal output electrically coupled to the first input. In some embodiments, the second input is coupled to ground.

"In another embodiment, a method for providing a bias voltage to a differential circuit configured to process signals at frequencies within a signal band above a pre-determined frequency, the differential circuit having a first signal input and a second signal input, the first signal input and second signal input together forming a differential node includes providing a bias source having a DC bias voltage output, the DC bias voltage output having a first output impedance at DC, and a second output impedance at frequencies within the signal band; providing a bias first resistance coupled between the bias voltage output and the first signal input so as to provide a DC bias voltage to the first signal input; and providing a second bias resistance coupled between the bias voltage output and the second signal input so as to provide the DC bias voltage to the second signal input, the magnitude of the first output impedance being less than 10 percent of the smaller of the first bias resistance and the second bias resistance, and the magnitude of the second output impedance being at least 200 percent of the larger of the first bias resistance and the second bias resistance.

"In some embodiments, the differential circuit is an amplifier. In some embodiments, the differential circuit is a buffer. In some embodiments, the differential circuit is an intermediate stage of an amplifier, a buffer, or a comparator. In some embodiments, the differential circuit is a pseudo-differential amplifier. In some embodiments, the differential circuit is a comparator.

"In another embodiment, a biasing circuit for providing bias voltage to a plurality of signal nodes in a differential circuit, which differential circuit is configured to process signals at frequencies above a pre-determined frequency within a signal band, the differential circuit having a first signal node and a second signal node, the first signal node and second signal node together forming a differential node, including a bias source having a DC voltage source, the DC voltage source producing a DC bias voltage, and an inductance having a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to the DC voltage source; a first bias resistor having a first bias resistance, the first bias resistor coupled between the second inductor terminal and the first signal node so as to provide a DC bias voltage to the first signal node; and a second bias resistor having a second bias resistance, the second bias resistor coupled between the second inductor terminal and the second signal node so as to provide the DC bias voltage to the second signal node, such that the DC voltage output and the inductance form a bias source having a first output impedance at a DC, and a second output impedance within the signal band, the magnitude of the first output impedance being less than 10 percent of the smaller of the magnitude of the first bias resistance and the magnitude of the second bias resistance, and the magnitude of the second output impedance being at least 200 percent of the larger of the magnitude of the first bias resistance and the second bias resistance, provided that the magnitude of the first output impedance is less than the magnitude of the magnitude of the second output impedance.

"In some embodiments, the circuit also includes a source of a differential signal having a first differential output and a second component output; a first coupling capacitor electrically coupled between the first component output and the first signal node, and a second coupling capacitor electrically coupled between the second component output and the second signal node, such that the first coupling capacitor and second coupling capacitor AC-couple the source from the differential processor."

For more information, see this patent: Rey-Losada, Daniel. Common Mode Bias Circuit. U.S. Patent Number 8803602, filed July 6, 2012, and published online on August 12, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8803602.PN.&OS=PN/8803602RS=PN/8803602

Keywords for this news article include: Analog Devices Inc., Medical Device Companies.

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Source: Journal of Engineering


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