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Researchers Submit Patent Application, "Nanostructured CIGS Absorber Surface for Enhanced Light Trapping", for Approval

August 21, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Sang, Baosheng (Austin, TX); Lu, Dingyuan (Austin, TX); Miller, Roy Mark (Austin, TX); Martinez, Casiano R. (Austin, TX); Kim, Minsik (Austin, TX); Moon, Changsup (Austin, TX); Stanbery, Billy J. (Austin, TX), filed on August 13, 2013, was made available online on August 7, 2014.

The patent's assignee is HelioVolt Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "Despite its remarkably high optical absorption coefficient, conventional CIGS absorbers are characterized by a planar top surface (relative to direction of solar radiation), requiring thicknesses on the order of 1-3.mu. in order to absorb all of the incident light and achieve high short-circuit current. These conventional planar CIGS absorbers suffer from relatively large dark recombination currents because the bulk of the semiconductor film buried beneath the surface receives relatively little infrared illumination due to shorter wavelength absorption near the planar surface on which the solar spectrum is incident, and because collection of carriers generated deeply within the absorber slab requires transport of minority carriers to the relatively distant planar junction. This reduces their efficiency compared to the potential efficiency of thinner absorber layers with non-planar surfaces that reduce reflection, trap light within the absorber through multiple internal reflections, and reduce the distance minority carriers must travel before crossing the junction where they become majority carriers and their recombination probability is thereby eliminated."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "There is a need for the following embodiments of the present disclosure. Of course, the present disclosure is not limited to these embodiments.

"According to an embodiment of the present disclosure, a method comprises: fabricating a layered precursor including: depositing a first film including a first indium gallium selenide compound on a substrate; then depositing a second film including a CuSe compound; then heating the substrate, the first film and the second film to convert the CuSe compound in the second film to a Cu.sub.2-xSe (0.2=

"These, and other, embodiments of the present disclosure will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating various embodiments of the present disclosure and numerous specific details thereof, is given for the purpose of illustration and does not imply limitation. Many substitutions, modifications, additions and/or rearrangements may be made within the scope of embodiments of the present disclosure, and embodiments of the present disclosure include all such substitutions, modifications, additions and/or rearrangements.

BRIEF DESCRIPTION OF THE DRAWINGS

"The drawings accompanying and forming part of this specification are included to depict certain embodiments of the present disclosure. A clearer concept of the embodiments described in this application will be readily apparent by referring to the exemplary, and therefore nonlimiting, embodiments illustrated in the drawings (wherein identical reference numerals (if they occur in more than one view) designate the same elements). The described embodiments may be better understood by reference to one or more of these drawings in combination with the following description presented herein. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale.

"FIG. 1 is an image of a CIGS absorber layer designed for light trapping.

"FIGS. 2A-2E are schematic diagrams showing exemplary, sequential steps to fabricate a CIGS absorber layer designed for light trapping.

"FIG. 3A, is an image of a plane view of a conventional morphology appropriately labeled 'prior art' and FIG. 3B is a cross-sectional image of a CIGS absorber designed for light trapping.

"FIG. 4A, is an image of a GIGS absorber designed for light trapping made with a rapid isothermal processor approach and FIG. 4B is an image of a CIGS absorber designed for light trapping made with a rapid optical processor method.

"FIGS. 5A-5C are images of a buffer layer conformally coupled to a CIGS absorber layer designed for light trapping.

"FIG. 6 illustrates results for quantum efficiency as a function of wavelength (nm) for a GIGS absorber layer designed for light trapping conformally coupled to a buffer layer.

"FIGS. 7A-7C are images of a transparent resistive oxide layer coupled to a buffer layer coupled to a GIGS absorber layer that is designed for light trapping. FIGS. 7D-7F are images of a transparent resistive oxide layer coupled to a buffer layer coupled to a GIGS absorber layer designed for light trapping."

For additional information on this patent application, see: Sang, Baosheng; Lu, Dingyuan; Miller, Roy Mark; Martinez, Casiano R.; Kim, Minsik; Moon, Changsup; Stanbery, Billy J. Nanostructured CIGS Absorber Surface for Enhanced Light Trapping. Filed August 13, 2013 and posted August 7, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6511&p=131&f=G&l=50&d=PG01&S1=20140731.PD.&OS=PD/20140731&RS=PD/20140731

Keywords for this news article include: Nanoscale, Nanotechnology, Emerging Technologies, HelioVolt Corporation.

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Source: Politics & Government Week


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