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Researchers Submit Patent Application, "Methods of Programming Multi-Level Cell Nonvolatile Memory Devices and Devices So Operating", for Approval

August 21, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Song, Jung-Ho (Suwon-si, KR); Kim, Su-Yong (Yongin-si, KR); Hwang, Sang-Won (Suwon-si, KR), filed on January 28, 2014, was made available online on August 7, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices based on whether data stored therein is retained after power is removed from the device. The nonvolatile memory device can include an Electrically Erasable and Programmable Read Only Memory (EEPROM).

"The EEPROM may operate in a program mode to write data to a memory cell, a read mode to read out the data stored in the memory cell and an erase mode to initialize a memory cell by erasing the stored data. In general, according to the Incremental Step Pulse Program (ISPP) scheme, the verify operation and reprogram operation after the verify operation can be repeated until the verification is completed.

"Programming of an Multi-Level Cell (MLC) provides for the storage of 2 (or more) bits of data in one memory cell. If N bits are stored in one MLC, the threshold voltage distribution of each MLC can be subdivided into 2.sup.N where each threshold voltage distribution expresses N bit data. For example, when 2 bits of data are stored in one memory cell, the threshold voltage distribution of the memory cell is subdivided into four levels. When a bit value '0' is written in the MLC represents program allow and a bit value '1' represents program inhibit, the states of the MLC having four threshold voltages may be represented as '11', '10', '01' and '00' according to the descending order of the threshold voltage. In this case, '11' represents the state of the MLC which remains erased without being programmed.

"At this time, a floating gate coupling may be applied to adjacent word lines while performing each step, so distribution distortion may occur. If the distribution distortion becomes severe, the program may fail, causing a read error."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Some example embodiments provide a method of programming in a multi-level nonvolatile memory device capable of minimizing influence of the word line coupling by reducing the maximum variation range of threshold voltage before and after a program by using a preprogram.

"Some example embodiments provide a method of programming in a multi-level nonvolatile memory device capable of adopting a preprogram scheme considering a word line coupling gain and a time overhead.

"According to example embodiments, a method of programming in a nonvolatile memory device is provide, where the nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps. The method includes performing a primary program from an erase level to a first target level with respect to the memory cells coupled to a selected word line; performing a preprogram from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, the preprogram level being larger than the erase level and smaller than the first target level; and performing a secondary program from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

"A distribution range of a threshold voltage of preprogrammed memory cells may be larger than a word line coupling gain and smaller than a value that is obtained by subtracting a word line coupling limit margin width from a maximum value of the second target level.

"The preprogram may be performed using a program pulse of a first program loop for performing the primary program.

"The preprogram may be performed using a preprogram pulse that is added before a program pulse of a first program loop for performing the primary program.

"The preprogram may be performed using a first program loop for performing the primary program.

"The preprogram may be performed using one or more preprogram loops that are added before a first program loop for performing the primary program.

"Each preprogram loop includes programming the preprogrammed memory cells using a preprogram pulse and verifying program states of the preprogrammed memory cells using a verify pulse, and the preprogram may be inhibited with respect to the preprogrammed memory cells having a threshold voltage level higher than a verify level of the verify pulse.

"The method may further includes performing the primary program and the preprogram with respect to the memory cells coupled to an adjacent word line, after performing the primary program and the preprogram with respect to the memory cells coupled to an adjacent word line and before performing the secondary program with respect to the preprogrammed memory cells coupled to the selected word line.

"The method may further includes performing the secondary program with respect to the preprogrammed memory cells coupled to the adjacent word line, after programming is completed with respect to the memory cells coupled to the selected word line.

"According to example embodiments, a method of programming in a nonvolatile memory device is provided, where the nonvolatile memory device includes a plurality of memory cells that are programmed into multiple states through at least two program steps. The method includes performing a primary program from an erase level to a first target level with respect to the memory cells coupled to a first word line; performing a preprogram from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the first word line, the preprogram level being larger than the erase level and smaller than the first target level; performing the primary program with respect to the memory cells coupled to a second word line adjacent to the first word line; and performing the preprogram with respect to the memory cells coupled to the second word line.

"The method may further includes performing a secondary program from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the first word line, after performing the primary program and the preprogram with respect to the memory cells coupled to the second word line.

"As described above, according to the programming method of the multi-level nonvolatile memory device of the example embodiments, variation of threshold voltage before and after the program can be reduced by the preprogram. That is, influence of the word line coupling can be reduced, thereby reducing the distribution distortion and read error.

"Effects of the example embodiments may not be limited to the above, and other effects may be clearly comprehended to those skilled in the art within the scope of the example embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

"Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

"FIG. 1 is a block diagram illustrating a nonvolatile memory device according to an example embodiment.

"FIG. 2 is a circuit diagram illustrating a memory cell array in the nonvolatile memory device of FIG. 1.

"FIG. 3 is a diagram for describing a general 4-level multi-step program method.

"FIG. 4 is a diagram for describing variation of cell threshold voltage caused by a word line coupling in a multi-step program operation.

"FIG. 5 is a diagram for describing a multi-step program operation employing a pulse preprogram scheme according to example embodiments.

"FIG. 6 is a diagram illustrating the distribution range of threshold voltage in a pulse preprogrammed state according to example embodiments.

"FIG. 7 is a flowchart illustrating a programming method according to example embodiments.

"FIG. 8 is a flowchart illustrating a subprogram in FIG. 7 according to example embodiments.

"FIG. 9 is a diagram for describing a use of a program pulse of a first program loop of a primary program as a preprogram pulse as an example of the subprogram of FIG. 8.

"FIG. 10 is a flowchart illustrating a subprogram in FIG. 7 according to another example embodiment.

"FIG. 11 is a diagram for describing a preprogram pulse added before a program pulse of a first program loop of a primary program as another example of the subprogram of FIG. 7.

"FIG. 12 is a flowchart illustrating a subprogram in FIG. 7 according to still another example embodiment.

"FIG. 13 is a diagram for describing a use of one or more program loops of a primary normal program as a preprogram loop.

"FIG. 14 is a flowchart illustrating a subprogram in FIG. 7 according to still another example embodiment.

"FIG. 15 is a diagram for describing a preprogram loop added before a first program loop of a primary program as an example of the subprogram of FIG. 14.

"FIG. 16 is a diagram illustrating the distribution range of threshold voltages in respective program steps for describing the multi-step program operation employing a preprogram loop scheme according to example embodiments.

"FIG. 17 is a diagram illustrating the distribution range of threshold voltage in a loop-preprogrammed state according to example embodiments.

"FIG. 18 is a diagram illustrating a program sequence according to example embodiments.

"FIG. 19 is a flowchart illustrating a programming method corresponding to the program sequence of FIG. 18.

"FIG. 20 is a block diagram illustrating a structure of a Solid State Disk (SSD) system including a flash memory device according to example embodiments.

"FIG. 21 is a block diagram illustrating a structure of a memory system according to example embodiments.

"FIG. 22 is a block diagram illustrating a structure of a computing system including a flash memory device according to example embodiments.

"FIG. 23 is a block diagram illustrating a memory module including at least one memory device according to example embodiments."

For additional information on this patent application, see: Song, Jung-Ho; Kim, Su-Yong; Hwang, Sang-Won. Methods of Programming Multi-Level Cell Nonvolatile Memory Devices and Devices So Operating. Filed January 28, 2014 and posted August 7, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4107&p=83&f=G&l=50&d=PG01&S1=20140731.PD.&OS=PD/20140731&RS=PD/20140731

Keywords for this news article include: Patents.

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