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Researchers Submit Patent Application, "Fabricating Method of Non-Volatile Memory Structure", for Approval

August 21, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Cheng, Chih-Chieh (Hsinchu, TW); Yan, Shih-Guei (Hsinchu, TW); Tsai, Wen-Jer (Hsinchu, TW), filed on January 25, 2013, was made available online on August 7, 2014.

The patent's assignee is Macronix International Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The embodiment of the invention relates to a memory structure and a fabricating method thereof and more particularly relates to a non-volatile memory structure and a fabricating method thereof.

"A memory is a semiconductor device designed for the purpose of storing information or data. As the functionalities of computer microprocessors become more and more powerful, programs and operations executed by the software are increasing correspondingly. As a consequence, the demand for high storage capacity memories is ever increasing. Among various memory products, the non-volatile memory allows repeated programming, reading, and erasure of data. Moreover, the stored data is retained even after power to the memory is removed. In light of the aforementioned advantages, the electrically-erasable programmable read-only memory has become one of the most popular memories in personal computers and other electronic equipment.

"A typical non-volatile memory has floating gates and control gates fabricated by using doped polysilicon. As the memory is programmed, electrons injected into the floating gate are uniformly distributed in the entire polysilicon floating gate. However, if the tunnel oxide layer under the polysilicon floating gate has defects, it can easily cause a leakage current in the device and affect the reliability of the device.

"Therefore, in order to solve the issue of current leakage in the non-volatile memory, a conventional method utilizes a charge trapping layer to replace the polysilicon floating gate. Another advantage obtained from replacing the polysilicon floating gate with the charge trapping layer is that the electrons are only stored in a portion of the charge trapping layer that is near the top of the source or the drain when the device is programmed. By changing the voltages applied to the control gate and the source region and the drain region at the two sides, a single charge trapping layer can have two groups of electrons with a Gaussian distribution, a single group of electrons with the Gaussian distribution, or no electrons. Accordingly, the non-volatile memory having the charge trapping layer, instead of the floating gate, is a non-volatile memory for storing 2 bits/cell. Generally speaking, data of 2 bits can be respectively stored on the left side (i.e. left bit) or the right side (i.e. right bit) of the charge trapping layer.

"However, a flash memory may suffer from a second bit effect. That is, when a reading operation is performed on the left bit, the reading operation is affected by the right bit; or when the reading operation is performed on the right bit, the reading operation is affected by the left bit. In addition, the length of the channel is reduced as the memory is miniaturized, which makes the second bit effect become more obvious and reduce the performance of the memory. Moreover, when the size of the memory is reduced, spacings between the elements therein are shortened as well. As a result, program disturbance may easily occur and impair the reliability of the memory device when a programming operation is performed on the neighboring memory."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "An embodiment of the invention provides a non-volatile memory structure for reducing the second bit effect and program disturbance that are generated during operation.

"Another embodiment of the invention provides a fabricating method for fabricating a non-volatile memory structure that has favorable performance and reliability.

"An embodiment of the invention provides a non-volatile memory structure, which includes a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.

"According to an embodiment of the invention, in the non-volatile memory structure, each of the charge storage structures includes a second dielectric layer, a charge trapping layer, and a third dielectric layer, which are arranged sequentially from the substrate.

"According to an embodiment of the invention, in the non-volatile memory structure, each of the stacked structures further includes a hard mask layer disposed on each of the charge storage structures.

"According to an embodiment of the invention, in the non-volatile memory structure, a width of the first conductive type doped region is less than a width of the charge storage structure, for example.

"According to an embodiment of the invention, in the non-volatile memory structure, a dopant concentration of the second conductive type doped region is greater than a dopant concentration of the first conductive type doped region, for example.

"According to an embodiment of the invention, in the non-volatile memory structure, a dopant depth of the second conductive type doped region is greater than a dopant depth of the first conductive type doped region, for example.

"According to an embodiment of the invention, in the non-volatile memory structure, a ratio of a width of the overlap region to the width of the charge storage structure is in a range of 1:30 to 1:5, for example.

"According to an embodiment of the invention, in the non-volatile memory structure, the width of the overlap region is 30 to 150 .ANG., for example.

"According to an embodiment of the invention, in the non-volatile memory structure, the conductive layer further covers the stacked structures.

"According to an embodiment of the invention, in the non-volatile memory structure, the first dielectric layer is further disposed between the stacked structures and the conductive layer.

"Another embodiment of the invention provides a fabricating method for fabricating a non-volatile memory structure, and the fabricating method includes the following steps. A first conductive type doped layer is formed in a substrate. A plurality of stacked structures are formed on the substrate, and each of the stacked structures includes a charge storage structure. A first dielectric layer is formed on the substrate between the adjacent stacked structures. A second conductive type doped region is formed in the substrate between the adjacent charge storage structures. The second conductive type doped region has an overlap region with each of the charge storage structures. In addition, the second conductive type doped region divides the first conductive type doped layer into a plurality of first conductive type doped regions that are separated from each other. A conductive layer is formed on the first dielectric layer.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, a method for forming the stacked structures includes the following steps. A second dielectric material layer, a charge trapping material layer, and a third dielectric material layer are sequentially formed on the substrate. A patterning process is performed on the third dielectric material layer, the charge trapping material layer, and the second dielectric material layer.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, the method for forming the stacked structures further includes the following steps. A hard mask material layer is formed on the third dielectric material layer. The patterning process is performed on the hard mask material layer.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, a width of the first conductive type doped region is less than a width of the charge storage structure, for example.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, a dopant concentration of the second conductive type doped region is greater than a dopant concentration of the first conductive type doped region, for example.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, a dopant depth of the second conductive type doped region is greater than a dopant depth of the first conductive type doped region, for example.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, a ratio of a width of the overlap region to the width of the charge storage structure is in a range of 1:30 to 1:5, for example.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, the width of the overlap region is 30 to 150 .ANG., for example.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, the first dielectric layer may cover the stacked structures.

"According to another embodiment of the invention, in the fabricating method of the non-volatile memory structure, the second conductive type doped region may be formed after or before forming the first dielectric layer.

"Based on the above, in the non-volatile memory structure disclosed in an embodiment of the invention, the charge storage structures used for storing charges are located at two sides of the second conductive type doped region and are separated from each other, and most of the programmed charge distribution is restricted within the charge storage structures in the overlap region. Consequently, the second bit effect and program disturbance that are generated during operation are reduced.

"Moreover, the fabricating method of the non-volatile memory structure disclosed in an embodiment of the invention is applicable to fabricating a non-volatile memory that has better performance and reliability.

"To make the aforementioned and other features and advantages of an embodiment of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

"The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.

"FIGS. 1A-1E are schematic cross-sectional views illustrating steps of fabricating a non-volatile memory structure according to an embodiment of the invention."

For additional information on this patent application, see: Cheng, Chih-Chieh; Yan, Shih-Guei; Tsai, Wen-Jer. Fabricating Method of Non-Volatile Memory Structure. Filed January 25, 2013 and posted August 7, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5680&p=114&f=G&l=50&d=PG01&S1=20140731.PD.&OS=PD/20140731&RS=PD/20140731

Keywords for this news article include: Macronix International Co. Ltd.

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