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Patent Issued for Self-Aligned Permanent On-Chip Interconnect Structure Formed by Pitch Splitting

August 20, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- International Business Machines Corporation (Armonk, NY) has been issued patent number 8795556, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Lin, Qinghuang (Yorktown Heights, NY).

This patent was filed on April 24, 2012 and was published online on August 5, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Optical lithography has been the workhorse to continuously shrink (or scale) semiconductor devices and their related interconnect structures. Traditional scaling by optical lithography has been achieved with one single exposure mostly by reduction in the wavelength of the light sources, new tool design (higher numerical aperture or NA), improved lithographic materials or a combination thereof. Recently, multiple patterning, particularly double patterning techniques, where one particular level of circuitry is patterned by exposing the wafer to a light source using two mask sets, has become increasingly necessary to maintain the pace of scaling at 193 nm optical wavelength. Typical double patterning (or pitch splitting) techniques, also referred to as double-exposure, double-etch schemes, require a lithographic imaging step, followed by a dry reactive ion etch (RIE) step into a sacrificial hardmask, followed by a second lithographic step, and yet a second RIE step into the hardmask. Finally, the double patterned images in the hardmask are transferred to the underlying substrate.

"An improvement over this double patterning scheme is referred to as a double-exposure, single-etch scheme. The double-exposure, single-etch scheme achieves improved resolution by two independent exposures to form a double patterned image in a single patterning film stack and thereafter the double patterned image is transferred into the underlying substrate utilizing a single etch. This double-exposure, single-etch process scheme is as follows: A first pattern is formed into a first photoresist film by a high-resolution lithographic processes known in the art. Next, a second photoresist is coated directly on top of the first pattern. The coating of the second photoresist does not degrade the first pattern since a proper solvent for the second photoresist is employed or an image stabilization process to treat the first pattern such as, for example, thermal cure, ultraviolet cure, or surface coating, is employed. A second pattern is then formed in the second photoresist to achieve pitch splitting and thus higher resolution. Finally, an integrated reactive ion etch is performed in which both the first and second photoresist patterns are transferred into the underlying film stack.

"The above mentioned double patterning scheme necessitates a significant increase in complexity, additional materials and tools, and the attendant increased manufacturing costs compared with a single exposure technique. Furthermore, the aforementioned double patterning scheme requires precise placement of the second exposure over the patterns formed by the first exposure. Any imperfect placement, or mis-alignment or overlay error, can cause degradation in performance or reliability or both of the resultant computer chips. Such mis-alignment is due to the limitation of the lithographic tool employed or processing errors.

"The present disclosure the problems associated with prior art double patterning and double-exposure, single etch patterning schemes with a single-exposure, no-etch, self-aligned pitch splitting process using a hybrid photo-patternable dielectric material."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "In this disclosure, a single-exposure-no-etch, self-aligned pitch splitting process using a hybrid photo-patternable dielectric material is employed to provide a self-aligned permanent on-chip interconnect structure. The process of the present application can reduce the fabrication steps, materials and tools as well as costs of fabricating an interconnect structure. The disclosed process also improves resolution with just one exposure, compared with two exposures of traditional double patterning, using a single-exposure-no-etch, self-aligned pitch splitting process with a hybrid photo-patternable dielectric material. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to an irradiation. The disclosed process can also mitigate overlay challenge associated with using a traditional double exposure, double patterning process. Moreover, the disclosed process can also reduce plasma induced dielectric damage during the fabrication of an interconnect structure (single or dual damascene).

"In particular, the process of the present disclosure includes the use of a hybrid photo-patternable dielectric (HPPD) material which can serve as both a photoresist material and as a permanent on-chip insulator, after patterning and curing. In the present process, self-aligned double patterns are formed utilizing a single exposure process. After patterning of the HPPD material, the patterned HPPD material can be converted into a permanent patterned on-chip material by curing.

"One aspect of the present disclosure relates to a method of fabricating an interconnect structure. In this aspect, the method includes forming a hybrid photo-patternable dielectric (HPPD) material atop a substrate. As mentioned above, the HPPD material has dual-tone properties with a parabola like dissolution response to an irradiation. The HPPD material is then image-wise exposed to an irradiation, wherein a self-aligned pitch split pattern is formed within the HPPD material. By 'self-aligned pitch split pattern' it is meant a pattern with minimum feature size about one half of the minimum feature size (pitch splitting) of a pattern formed otherwise with single exposure using the same mask and tool set wherein the pitch split pattern is aligned (placed) without the need for external assistance as in traditional double exposure, double patterning. After the image-wise exposing step, a portion of the self-aligned pitch split pattern is removed to provide a self-aligned pitch split patterned HPPD material having at least one opening therein. The self-aligned split pitch patterned HPPD material is converted into a cured and patterned permanent on-chip dielectric material having the at least one opening therein. Next, the at least one opening is filled with at least an electrically conductive material.

"In one embodiment, the HPPD material includes a blend of a positive-tone component and a negative-tone component. During the image-wise exposure step, the positive-tone component of the HPPD material forms a positive-tone latent image and the negative-tone component of the HPPD material forms a negative-tone latent image during just one exposure. Next, part of the positive-tone latent image or part of the negative-tone latent image is removed to provide a self-aligned pitch split patterned HPPD material having at least one opening therein. The self-aligned pitch split patterned HPPD material is then converted into a cured and patterned permanent on-chip dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filled with at least an electrically conductive material.

"In another embodiment of the present disclosure, the HPPD material that can be employed comprises a blend of a photoacid generator and a photobase generator in a chemically amplified positive-tone or negative-tone resist.

"Another aspect of the present disclosure relates to a method of fabricating an interconnect structure which further includes a step of trimming (or cutting) and/or filling the dielectric after formation of the self-aligned pitch split patterned HPPD material. This trimming step provides proper wire routing in the finished interconnect. The trimming step can be achieved with lithography or lithography in combination with reactive ion etching.

"Another aspect of the present disclosure relates to a method of forming an interconnect structure that includes forming a HPPD material atop a substrate. The HPPD material is then image-wise exposed to an irradiation, wherein a first self-aligned pitch split pattern is formed within the HPPD material. After the image-wise exposing step, a portion of the first self-aligned pitch split pattern is removed to provide a first self-aligned pitch split patterned HPPD material having at least one opening therein. Another HPPD material is formed atop the first self-aligned pitch split patterned HPPD material having the at least one opening therein. The another HPPD material is image-wise exposed to an irradiation, wherein a second self-aligned pitch split pattern is formed within the another HPPD material. After the image-wise exposing step, a portion of the second self-aligned pitch split pattern is removed to provide a second self-aligned pitch split patterned HPPD material having at least one second opening therein. The first and second self-aligned split pitch patterned HPPD materials are converted into cured and patterned permanent on-chip dielectric materials having the at least one first and one second openings therein. Next, the at least one first and one second openings are filled with at least an electrically conductive material.

"Another aspect of the present disclosure relates to a HPPD composition which can be used to form the HPPD material mentioned above. In one embodiment, the HPPD composition includes at least one positive-tone component including a positive-tone polymer, a positive-tone copolymer, or a blend of positive-tone polymers and/or positive-tone copolymers having one or more acid sensitive positive-tone functional groups; at least one negative-tone component including a negative-tone polymer, a negative-tone copolymer, or a blend of negative-tone polymers and/or negative-tone copolymers having one or more acid sensitive negative-tone functional groups; at least one photoacid generator; and at least one solvent that is compatible with the positive-tone and negative-tone components.

"In another embodiment, the HPPD composition includes a chemically amplified positive-tone or negative-tone resist; a blend of a photoacid generator and a photobase generator and a solvent. In one instance of this embodiment, the HPPD composition can include at least one positive-tone polymer, a positive-tone copolymer, or a blend of positive-tone polymers and/or positive-tone copolymers having one or more acid sensitive positive-tone functional groups; a blend of photoacid generator and a photobase generator; and a solvent. In another instance of this embodiment, the HPPD composition includes at least one negative-tone polymer, a negative-tone copolymer, or a blend of negative-tone polymers and/or negative-tone copolymers having one or more acid sensitive negative-tone functional groups; a blend of photoacid generator and a photobase generator; and a solvent.

"A still further aspect of the present disclosure relates to an interconnect structure which includes a line level having at least one electrically conductive filled line embedded within a dielectric material located directly above a via level, said via level includes a cured and patterned permanent on-chip hybrid photo-patternable dielectric material that has an electrically conductive filled self-aligned via embedded therein, wherein said electrically conductive filled self-aligned via comprises a permanent dielectric spacer separating neighboring electrically conductive filled regions of said self-aligned via."

For the URL and additional information on this patent, see: Lin, Qinghuang. Self-Aligned Permanent On-Chip Interconnect Structure Formed by Pitch Splitting. U.S. Patent Number 8795556, filed April 24, 2012, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8795556.PN.&OS=PN/8795556RS=PN/8795556

Keywords for this news article include: International Business Machines Corporation.

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Source: Journal of Engineering


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