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Patent Issued for Junction-Isolated Blocking Voltage Devices with Integrated Protection Structures and Methods of Forming the Same

August 20, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- Analog Devices, Inc. (Norwood, MA) has been issued patent number 8796729, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Clarke, David J (Patrickswell, IE); Salcedo, Javier Alejandro (North Billerica, MA); Moane, Brian B (Raheen, IE); Luo, Juan (San Jose, CA); Murnane, Seamus (Bruff, IE); Heffernan, Kieran K (Patrickswell, IE); Twomey, John (Fountainstown, IE); Heffernan, Stephen Denis (Tipperary, IE); Cosgrave, Gavin Patrick (Wexford, IE).

This patent was filed on November 20, 2012 and was published online on August 5, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Embodiments of the invention relate to electronic systems, and more particularly, to protection systems for integrated circuits (ICs).

"Certain electronic systems can be exposed to a transient electrical event, or an electrical signal of a relatively short duration having rapidly changing voltage and high power. Transient electrical events can include, for example, electrostatic discharge (ESD) events and/or electromagnetic interference (EMI) events.

"Transient electrical events can damage integrated circuits (ICs) inside an electronic system due to overvoltage conditions and/or high levels of power dissipation over relatively small areas of the ICs. High power dissipation can increase IC temperature, and can lead to numerous problems, such as gate oxide punch-through, junction damage, metal damage, and surface charge accumulation. Moreover, transient electrical events can induce latch-up (in other words, inadvertent creation of a low-impedance path), thereby disrupting the functioning of the IC and potentially causing permanent damage to the IC. Thus, there is a need to provide an IC with protection from such transient electrical events, such as during IC power-up and power-down conditions."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "In one embodiment, an apparatus includes a p-type substrate, a first p-type well disposed in the p-type substrate, a first n-type well disposed in the p-type substrate adjacent the first p-type well, a second p-type well disposed in the p-type substrate, and an n-type isolation layer beneath the first p-type well, the second n-type well, and at least a portion of the second p-type well. The first p-type well includes at least one p-type active region and at least one n-type active region electrically connected to a first terminal. Additionally, the first n-type well includes at least one p-type active region and at least one n-type active region electrically connected to a second terminal. Furthermore, the second p-type well includes at least one p-type active region and at least one n-type active region electrically connected to a third terminal. The first p-type well and the first n-type well are configured to operate as a blocking diode. Additionally, the at least one p-type active region of the first n-type well, the first n-type well, the first p-type well, and the at least one n-type active region of the first p-type well are configured to operate as a PNPN silicon controlled rectifier. Furthermore, the at least one n-type active region of the first p-type well, the first p-type well, the n-type isolation layer, the second p-type well, and the at least one n-type active region of the second p-type well are configured to operate as an NPNPN bidirectional silicon controlled rectifier.

"In another embodiment, an apparatus includes a blocking diode, a first PNP bipolar transistor, a first NPN bipolar transistor, a second NPN bipolar transistor, and a bidirectional PNP bipolar transistor. The blocking diode includes an anode electrically connected to a first terminal and a cathode electrically connected to a second terminal. Additionally, the first PNP bipolar transistor includes an emitter electrically connected to the second terminal, a base, and a collector. Furthermore, the first NPN bipolar transistor includes an emitter electrically connected to the first terminal, a base electrically connected to the collector of the first PNP bipolar transistor, and a collector electrically connected to the base of the first PNP bipolar transistor. Additionally, the second NPN bipolar transistor includes an emitter electrically connected to a third terminal, a base, and a collector. Furthermore, the bidirectional PNP bipolar transistor includes an emitter/collector electrically connected to the base of the second NPN bipolar transistor, a collector/emitter eclectically connected to the base of the first NPN bipolar transistor, and a base electrically connected to the collectors of the first and second NPN bipolar transistors. The first PNP bipolar transistor and the first NPN bipolar transistor are configured to operate as a PNPN silicon controlled rectifier. Additionally, the first NPN bipolar transistor, the bidirectional PNP bipolar transistor, and the second NPN bipolar transistor are configured to operate as an NPNPN bidirectional silicon controlled rectifier.

"In another embodiment, a method of making a blocking device is provided. The method includes forming a first p-type well in a p-type substrate, forming at least one p-type active region and at least one n-type active region in the first p-type well, forming a first n-type well in the p-type substrate adjacent the first p-type well, forming at least one p-type active region and at least one n-type active region in the first n-type well, forming a second p-type well in the p-type substrate, forming at least one p-type active region and at least one n-type active region in the second p-type well, and forming an n-type isolation layer beneath the first p-type well, the second n-type well, and at least a portion of the second p-type well. The first p-type well and the first n-type well are configured to operate as a blocking diode. Additionally, the at least one p-type active region of the first n-type well, the first n-type well, the first p-type well, and the at least one n-type active region of the first p-type well are configured to operate as a PNPN silicon controlled rectifier. Furthermore, the at least one n-type active region of the first p-type well, the first p-type well, the n-type isolation layer, the second p-type well, and the at least one n-type active region of the second p-type well are configured to operate as an NPNPN bidirectional silicon controlled rectifier."

For the URL and additional information on this patent, see: Clarke, David J; Salcedo, Javier Alejandro; Moane, Brian B; Luo, Juan; Murnane, Seamus; Heffernan, Kieran K; Twomey, John; Heffernan, Stephen Denis; Cosgrave, Gavin Patrick. Junction-Isolated Blocking Voltage Devices with Integrated Protection Structures and Methods of Forming the Same. U.S. Patent Number 8796729, filed November 20, 2012, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8796729.PN.&OS=PN/8796729RS=PN/8796729

Keywords for this news article include: Silicon, Analog Devices Inc., Medical Device Companies.

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Source: Journal of Engineering


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