News Column

Patent Issued for Integrated Circuit Layout Design Methodology with Process Variation Bands

August 20, 2014

By a News Reporter-Staff News Editor at Journal of Engineering -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Robles, Juan Andres Torres (Wilsonville, OR), filed on May 6, 2005, was published online on August 5, 2014.

The assignee for this patent, patent number 8799830, is Mentor Graphics Corporation (Wilsonville, OR).

Reporters obtained the following quote from the background information supplied by the inventors: "In a conventional integrated circuit design process, a circuit designer begins with a conceptual idea of what functions an integrated circuit is to perform. The circuit designer then creates a circuit design on a computer and verifies it using one or more simulation tools to ensure that the circuit will operate as desired. The design at this stage may be represented by what is commonly viewed as a circuit schematic, but may also be represented by higher level abstractions within the computer.

"These abstract designs are then converted to physical definitions of the circuit elements to be fabricated. These definitions, often called the circuit layout, represent the geometric boundaries for the physical devices to be fabricated--transistor gates, capacitors, resistive interconnecting wires, etc. A number of data formats have been created to represent these physical layouts, including GDS-II and OASIS.TM.. Often, each physical layer of the circuit has a corresponding data layer to represent the polygonal boundaries of the elements in that layer.

"Once the circuit layout has been defined, additional verification checks are performed. Some of these verification checks are to insure that the physical structures will correctly represent the desired electrical behavior. This is commonly called a LVS, for Layout vs. Schematic or Layout vs. Source. Additional extraction of parasitic resistances and capacitances can be done, and the dynamic behavior of the circuit can be estimated for the layout as well. This step is traditionally called parasitic extraction.

"Other verification checks are carried out to ensure that the circuit layout can be manufactured with a particular process. For example, the layout may be subject to one or more design rule checks (DRCs) to ensure that the circuit does not contain any violations of circuit element placement or configurations that cannot be manufactured by the specified manufacturing process. In addition, resolution enhancement techniques (RETs), such as optical and process correction (OPC), may be applied to pre-compensate for the expected optical distortions that occur in the photolithographic process. The verified and OPC corrected layout data is then used to make a number of photolithographic masks or reticles that are used in the selected photolithographic process to image patterns on a semiconductor wafer in order to manufacture the desired circuit.

"While the above methodology works well for manufacturing integrated circuits under expected photolithographic process conditions, these process conditions can vary. For example, variations can occur in the focus of the image on the wafer, the dose of illumination light through the mask or reticle, the placement of a stepper, as well as other process conditions that affect how the circuit will be created on the wafer. In the past, there has not been a reliable method of taking into account the process variations that may occur when designing a circuit so that the circuit will operate as intended regardless of the conditions used to actually manufacture the circuit. As such, there is a need for a system that can consider and compensate for expected process variations during the design and verification procedure so that the layout can be made more robust and easier to manufacture."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "To address the problems discussed above, the present invention is a method for verifying and/or compensating IC layouts for expected variations that occur in photolithographic processing. In accordance with one embodiment of the present invention, objects to be created on a wafer are modeled to determine ranges in the way the objects would be printed on the wafer under a variety of process conditions. In one embodiment, the ranges are stored as process variation bands (PV-bands) that specify the smallest and largest dimensions of an object that may be expected to print on a wafer. The PV-bands are analyzed by one or more rules to see if the circuit can be manufactured with the expected process conditions.

"In accordance with an embodiment of the invention, different IC layouts can be ranked by their manufacturability in accordance with the PV-bands created for the objects. In another embodiment of the invention, the PV-bands can be used to determine when an IC layout is acceptable for manufacture."

For more information, see this patent: Robles, Juan Andres Torres. Integrated Circuit Layout Design Methodology with Process Variation Bands. U.S. Patent Number 8799830, filed May 6, 2005, and published online on August 5, 2014. Patent URL:

Keywords for this news article include: Mentor Graphics Corporation.

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Source: Journal of Engineering

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