News Column

"Optimizing Designs of Integrated Circuits" in Patent Application Approval Process

August 19, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent application by the inventors Vujkovic, Jovanka Ciric (San Jose, CA); McElvain, Kenneth S. (Menlo Park, CA), filed on March 28, 2014, was made available online on August 7, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Synopsys, Inc.

The following quote was obtained by the news editors from the background information supplied by the inventors: "For the design of circuits on integrated circuits (ICs), designers often employ computer aided design techniques. Standard languages known as Hardware Description Languages (HDLs) have been developed to describe circuits to aid in the design and simulation of complex circuits. Several HDLs, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL), or the behavioral level using abstract data types.

"In designing circuits using HDL compilers, designers first describe circuit elements in HDL source code and then compile the source code to produce synthesized RTL netlists. The RTL netlists correspond to schematic representations of circuit elements. The circuits containing the synthesized circuit elements are often optimized to improve timing relationships and eliminate unnecessary or redundant logic elements. Such optimization typically involves substituting different gate types or combining and eliminating gates in the circuit. FIG. 1 shows a representative flow for designing certain types of ICs, such as Field Programmable Gate Arrays (FPGAs) which have a predetermined architecture, referred to as a target architecture. Operation 101 involves receiving a description (e.g. a description written in HDL) of an IC by a compiler which, in operation 103, performs a synthesis from the HDL description to an RTL description. In operation 105, the RTL description is mapped to a target architecture, such as the architecture of a Xilinx FPGA, and optimization within the target architecture is performed. After optimization is completed, a netlist for the target architecture is generated. Various methods and systems for computer aided design of ICs are described in U.S. Pat. Nos. 6,438,735; 6,449,762; and 6,973,632, all of which are incorporated herein by reference.

"FIG. 2 shows further details regarding a method, in the prior art, for optimizing a design of an IC. In operation 151, the loads which are driven by a particular component are determined, and in operation 153, a most critical load, of those loads, is determined. Then the particular critical component is replicated (operation 155) and the most critical load is connected (operation 157) to the replicated critical component. This will tend to reduce fanout at the source of the wiring net from the original critical component. The load is considered critical if it adversely affects timing constraints or requirements for the IC (or if it has negative slack), and the component is considered critical because it is driving the critical load. The slack of the IC is then recomputed in operation 159 and it is determined whether slack has improved (operation 161). If the slack has not improved, then the replication is discarded (operation 163) and processing returns to operation 151. If the slack has improved, then processing returns from operation 161 to operation 151 as shown in FIG. 2 to optimize other paths having other critical components. FIGS. 3A, 3B, and 3C show an example of the optimization method of FIG. 2.

"FIG. 3A shows a representation of at least a portion of an integrated circuit which may be designed according to the method of FIG. 1, with an optimization performed according to the method of FIG. 2. The design at this stage shown in FIG. 3A includes 9 switch matrices (SM) on the representation 201 of the integrated circuit. Switch matrices are common interconnection devices used on certain types of field programmable gate arrays, such as gate arrays from Xilinx. The switch matrices 202-210 allow for the interconnection of various components, such as driver components which output signals to loads which receive those signals. The design shown in FIG. 3A includes one driver 215 and 7 loads, L1-L7. In particular, driver 215 drives loads 216-222 through the routing net shown in FIG. 3A which includes wires W1, W2, and W3. The routing net includes those three wires which are existing wire resources on the IC. The switches on the switch matrix 209 through which the wires are connected are labeled SW1, SW2, and SW3, and the switch at the driver is labeled SWD. The critical loads in the design are L1, L2, L3 and L4 in the order of criticality, most critical being first. The delay of the net on each load depends on the wire delay, the switch delay and the fanout at each switch. The fanout at switch SWD is equal to 3 because there are 3 wires going to switches SW1, SW2, and SW3, which contribute with their capacitances to the wire delay. The total fanout of the net from driver D215 is equal to 7, but the root fanout at the switch SWD is only 3. Further details showing the root fanout at switch SWD is shown in FIG. 3B which shows the driver component 215 providing an input to the switch matrix 209 which is received by a driver 230 which in turn drives 3 pass gates (225, 226 and 227) in the switch SWD as shown in FIG. 3B. Each pass gate has a parasitic capacitance, an example of which is shown as parasitic capacitance 231 on the pass gate 225. These parasitic capacitances add to the delay at the root fanout. It will be appreciated that the driver component 215 may be one of a variety of different logic components, such as a flip-flop, a lookup table or other types of logic, including digital logic circuits.

"Previous methods for replication were concentrating at reducing the fanout, particularly the fanout at the root of the net, without paying attention at how the net is wired using existing wiring resources. For example, if we want to reduce the fanout by isolating the critical loads L1 and L2, the driver D can be replicated and the copied driver 215A can drive the rest of the loads. The total fanout of the net driven from the driver 215 will be 2 (down from 7) and the total fanout of the net driven from driver 215A will be 5. This is depicted in FIG. 3C. However, in terms of delay, little will be changed for critical loads L3 and L4 because the root delay of the net driven from driver 215A is still 3 as before replication, and the delay of the switch 254 and the wire W1A which is connecting loads L3 and L4 will be bigger if the faster wire W1 was taken to connect to L1 and L2.

"It is desirable to provide improved automated circuit design techniques, including techniques which include improved routing and optimization techniques which are described herein."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The present inventions relate to various methods and apparatuses for designing an integrated circuit, and particularly to automated design using a data processing system to design one or more integrated circuits. According to one aspect of the present inventions, an exemplary method for designing an integrated circuit includes routing, at a first routing level as part of the process of designing the IC, connections on a representation of the IC using a first set of wiring resources and marking wiring resources as used once the wiring resources within the first set have been used for routing and routing, at a second routing level using a second set of wiring resources in the representation of the IC, connections on the IC without checking whether wiring resources within the second set have been previously used to route connections, wherein wiring resources in the second set differ, on average, in physical size from wiring resources in the first set. Typically, the wiring resources in the second set are, on average, longer than wiring resources within the first set and the routing, which uses the second set, is performed without marking wiring resources within the second set as reserved once those wiring resources have been used as part of a routing operation.

"According to another aspect of the present inventions, an exemplary method includes determining a fanout of a driving component in a representation of the IC being designed, determining for the driving component the loads in the representation of the IC, driven by the driving component, determining the use of existing wire resources used to connect the loads to the driving component, and optimizing, based on the use of existing wiring resources and the fanout of the driving component and the loads being driven by the driving component, a design of the IC. Typically, the optimizing includes determining whether to reduce fanout at the driving component by replicating the driving component, and the replicating is performed automatically by a data processing system which is configured with a machine-readable medium to perform the replicating.

"According to another aspect of the present inventions, an exemplary method includes determining, as part of a process of designing an integrated circuit, a routing net from a load to a driving component and determining available places for a replicated version of the driving component, and creating, in the representation of the integrated circuit, the replicated version of the driving component based on the routing net and the available places and creating connections, in the representation, between the replicated version and the load. This method may be used to perform load-based replication in which the replication is performed by backtracking from a critical load through the available wires and by examining available places for the replicated driver. Further, other critical loads in the area which may be driven by the same replicated driver may also be connected through a progressive routing method described below.

"According to another aspect of the inventions described herein, an exemplary method includes replicating, as part of a process of designing an integrated circuit, a component in a representation of the IC and labeling the component as a replicated component having an output which is equivalent to an output of the component, and routing, in the representation, connections between the replicated component and the loads of the replicated component, and determining whether to use the replicated component as a source to drive at least one existing load of the component. At least certain embodiments of this aspect allow routing, in order to drive loads, from equivalent sources rather than the original source. By placing a tag on the replicated instances throughout the synthesis process, it is possible to identify equivalent sources which have been previously replicated so that routing operations may use those sources rather than an original source.

"According to another aspect of the present inventions described herein, an exemplary method includes determining whether a value for a wiring delay should be adjusted based upon a geometry of a wiring net in a representation of an integrated circuit being designed, and adjusting the value if the geometry is of a first type, and determining routing decisions, in the process for designing the integrated circuit, based on the value after the adjusting. This exemplary embodiment may be used to adjust for characterized wiring delays, which may be either measured or estimated, based upon whether a particular long distance wiring net is primarily a straight line through groups of switching matrices or a staircased path through another group of switching matrices.

"The present inventions provide computer systems which are capable of performing various methods of the inventions, and the inventions also provide computer readable media, such as machine-readable media, which contain executable program instructions which when executed by a data processing system, such as a computer system, cause the data processing system to perform one or more of the methods described herein. Other features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

"The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

"FIG. 1 is a flowchart which illustrates a process of HDL synthesis which may be used in at least certain embodiments of the present inventions.

"FIG. 2 is a flowchart which shows a prior art method for optimizing a design of an integrated circuit in an automated computer-aided design system.

"FIG. 3A shows a representation of an integrated circuit during an automated design process.

"FIG. 3B shows further detail within the switching matrix of the design shown in FIG. 3A.

"FIG. 3C shows the result of an optimization in the prior art performed according to the method shown in FIG. 2.

"FIG. 4 is a flowchart which illustrates one exemplary embodiment of the inventions for performing an optimization of an integrated circuit design.

"FIG. 5 shows a representation of an optimization resulting from one embodiment of the method shown in FIG. 4.

"FIG. 6 is a flowchart which illustrates a particular embodiment for optimizing an integrated circuit design in which root fanout is reduced based at least in part upon knowledge about the existing wiring net which is coupled to the root.

"FIG. 7 is a flowchart which illustrates an exemplary embodiment of another aspect of the present inventions described herein.

"FIG. 8 shows the layout of interconnections in at least certain types of ICs.

"FIG. 9 is a flowchart which illustrates an exemplary method of a routing process according to certain embodiments of the present invention.

"FIG. 10 is another flowchart showing a particular example of a routing process which is similar to the method shown in FIG. 9 and which may use the architecture of an integrated circuit such as that shown in FIG. 8.

"FIGS. 11A, 11B and 11C illustrate the process of designing a particular integrated circuit in a sequence in time.

"FIG. 12 is a flowchart which illustrates an exemplary method according to certain embodiments described herein, which method may produce the changes shown in FIGS. 11A, 11B and 11C.

"FIG. 13 shows an example of a layout of an integrated circuit having a plurality of switch matrices.

"FIG. 14 is a flowchart which illustrates an exemplary method according to certain embodiments of the present invention which adjust wiring delay based upon the geometry of a routing net, such as the two different geometries shown in FIG. 13.

"FIG. 15 is a block diagram of a data processing system, such as a computer system, that may be used to implement one or more of the embodiments described herein and may include one or more forms of machine-readable media which store executable program instructions which cause the data processing system to perform one or more of the methods described herein."

URL and more information on this patent application, see: Vujkovic, Jovanka Ciric; McElvain, Kenneth S. Optimizing Designs of Integrated Circuits. Filed March 28, 2014 and posted August 7, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=246&p=5&f=G&l=50&d=PG01&S1=20140731.PD.&OS=PD/20140731&RS=PD/20140731

Keywords for this news article include: Synopsys Inc, Information Technology, Information and Data Processing.

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