News Column

"Multiresolution Mask Writing" in Patent Application Approval Process

August 21, 2014

By a News Reporter-Staff News Editor at Politics & Government Week -- A patent application by the inventor Sahouria, Emile Y. (Sunnyvale, CA), filed on August 14, 2013, was made available online on August 7, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Mentor Graphics Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a 'design flow.' The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware 'tools' verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.

"Several steps are common to most design flows for integrated microcircuits.

"Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as 'functional verification.'

"After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as 'formal verification.'

"Once the relationships between circuit devices have been established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a 'layout' design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components (e.g., contacts, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as 'place and route' tools), such as Mentor Graphics'IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.

"With a layout design, each physical layer of the circuit will have a corresponding layer representation in the design, and the geometric elements described in a layer representation will define the relative locations of the circuit device components that will make up a circuit device. Thus, the geometric elements in the representation of an implant layer will define the doped regions, while the geometric elements in the representation of a metal layer will define the locations in a metal layer where conductive wires will be formed to connect the circuit devices. In addition to integrated circuit microdevices, layout design data also is used to manufacture other types of microdevices, such as microelectromechanical systems (MEMS). Typically, a designer will perform a number of analyses on the layout design data. For example, with integrated circuits, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, the layout design may be modified to include the use of redundant geometric elements or the addition of corrective features to various geometric elements, to counteract limitations in the manufacturing process, etc.

"After the layout design has been finalized, then it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. Masks and reticles are typically made using tools that expose a blank reticle to an electron or laser beam. Most mask writing tools are able to only 'write' certain kinds of polygons, however, such as right triangles, rectangles or other trapezoids. Moreover, the sizes of the polygons are limited physically by the maximum beam aperture size available to the tool. Accordingly, larger geometric elements in the layout design, or geometric elements that are not basic right triangles, rectangles or trapezoids (which typically is a majority of the geometric elements in a layout design) must be 'fractured' into the smaller, more basic polygons, sometimes called 'shots,' that can be written by the mask or reticle writing tool.

"Once the layout design has been fractured, then the fractured layout design data can be converted to a format compatible with the mask or reticle writing tool. Examples of such formats are MEBES, for raster scanning machines manufactured by ETEC, an Applied Materials Company, the '.MIC' format from Micronics AB in Sweden, and various vector scan formats for Nuflare, JEOL, and Hitachi machines, such as VSB12 or VSB12. The written masks or reticles can then be used in a photolithographic process to expose selected areas of a wafer in order to produce the desired integrated circuit devices on the wafer.

"During a conventional mask writing process, a mask writer may make multiple passes of exposure over the mask substrate, with each pass writing the same pattern of shots. The reasons for using multiple mask writing passes are varied, and include controlling placement errors due to mechanical stage movement, reducing line edge roughness by limiting shot noise magnitude, and increasing the amount of energy deposited per area in the presence of various per-shot constraints. With a conventional mask writing process, however, the total write time is dependent upon the number of shots being written, and can be substantial. Accordingly, the industry is continuously trying to reduce the total write time for forming lithographic masks."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventor's summary information for this patent application: "Aspects of the invention relate to mask writing techniques that employ multiple masking writing passes. According to various implementations of the invention, a first writing pass is made to write a first shot pattern having a first resolution. A second writing pass is then made to write a second shot pattern having a second resolution finer than the first resolution, such that the second shot pattern substantially overlaps with the first shot pattern on the mask substrate. With various implementations of the invention, the shot pattern with the coarser resolution can be formed from fewer shots than a corresponding conventional shot pattern, allowing it to be written more quickly than a corresponding conventional shot pattern. Moreover, the overlap of the first, coarse shot pattern with the second, finer shot pattern can be selected so that the first, coarse shot pattern combines with the second, finer shot pattern to form a desired shot pattern on the mask substrate. According to various implementations of the invention, the two patterns must be defined jointly with the use of a MPC tool.


"FIGS. 1 and 2 illustrate a computing system that may be employed to implement a mask writing system according to various embodiments of the invention.

"FIG. 3 illustrates the overlap of a course shot pattern and a fine shot pattern that may be provided according to various embodiments of the invention.

"FIGS. 4A and 5A illustrate top-down views of mask edges from two passes for a larger maximum deviation and a smaller maximum deviation, respectively.

"FIGS. 4B and 5B illustrate the image cross sections at the indicated cut lines in FIGS. 4A and 5A, respectively.

"FIG. 6 illustrates a graph showing the results of overexposing a multiresolution test pattern on a mask writer.

"FIG. 7 illustrates the mask data processing (MDP) flow that may be implemented for multiresolution mask writing according to various embodiments of the invention.

"FIG. 8A illustrates a histogram of edge placement errors measured using an MPC verification function.

"FIG. 8B illustrates the results of a simulation in which both exposure dose and shot placement are varied.

"FIG. 9 illustrates an example of a small mask layout.

"FIG. 10 illustrates the corresponding multiresolution shot patterns for a case where there is no error, and the arrow marks the field soft boundary.

"FIG. 11 illustrates the corresponding multiresolution shots in which the lower left field of the coarse writing pass was placed with a 0.2 degree counter clockwise rotation.

"FIG. 12 illustrates the simulated images for both writing methods shown in FIGS. 10 and 11 in the presence of the field placement error.

"FIG. 13 illustrates that simulation-based verification is required in some instances to distinguish between various potential sources of error."

URL and more information on this patent application, see: Sahouria, Emile Y. Multiresolution Mask Writing. Filed August 14, 2013 and posted August 7, 2014. Patent URL:

Keywords for this news article include: Software, Mentor Graphics Corporation.

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Source: Politics & Government Week

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