News Column

"Level-Estimation in Multi-Level Cell Memory" in Patent Application Approval Process

August 19, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent application by the inventors Mittelholzer, Thomas (Zurich, CH); Papandreou, Nikolaos (Thalwil, CH); Pozidis, Charalampos (Thalwil, CH), filed on January 27, 2014, was made available online on August 7, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to International Business Machines Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "This invention relates generally to level-estimation in multi-level cell memory, and more particularly to methods and apparatus for determining reference signal levels corresponding to respective levels of multi-level memory cells. These reference signal levels provide the basis for detecting stored codewords in memory read operations.

"In multi-level cell (MLC) memory, the fundamental storage unit (the 'cell') can be set to q>2 different states, or 'levels', permitting storage of more than one bit per memory cell. Detection of stored data relies on identifying the different cell levels on readback. In solid-state memory such as flash memory and phase change memory (PCM), for example, the different cell levels exhibit different electrical resistance characteristics which can be detected via current or voltage measurements on the cells. When writing information in MLC memory, each cell can be used to store a q.sup.ary symbol with each of the q possible symbol values being represented by a different cell level. On readout of multi-level cells, the read signal level is compared with a set of reference signal levels indicative of the q cell levels in order to determine which level each cell is set to and thus detect the stored symbol value."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "One embodiment of an aspect of the present invention provides a method for determining reference signal levels corresponding to respective levels of q-level memory cells, the cells storing respective symbols, each of which has one of q symbol values, of N-symbol codewords of a predefined codeword set, where q>2. The method comprises:

"reading the memory cells storing a group of codewords to obtain respective read signals each comprising N signal components corresponding to respective symbols of a codeword;

"ordering the components of each read signal according to signal level to produce an ordered read signal;

"ordering correspondingly-positioned components of the ordered read signals according to signal level to produce ordered component sets for respective component positions in a said ordered read signal;

"partitioning each ordered component set into subsets corresponding to respective memory cell levels, wherein the subsets of the ordered component sets contain respective numbers of components dependent on predefined probabilities of occurrence of different symbol values at different positions in a said codeword whose symbols are ordered according to symbol value; and

"determining the reference signal level corresponding to a respective memory cell level in dependence on the signal components in the subsets corresponding to that memory cell level.

"Methods embodying this invention provide for level-estimation in MLC memory storing length-N, q.sup.ary-symbol codewords whose symbols are stored in respective q-level memory cells. A plurality of stored codewords are read at a time, and the resulting read signals for this group of codewords are processed to determine current reference signal levels for respective levels of the q-level memory cells. Like the technique of our international patent application referenced above, the components of each read signal are first ordered according to signal level (e.g. in order of increasing signal level) to produce an ordered read signal. However, a further ordering process is then performed for correspondingly-positioned components of the ordered read signals, i.e. components at equivalent positions in the N-component sequences of the ordered read signals. Each of the resulting ordered component sets is then partitioned into subsets corresponding to respective memory cell levels. The size (i.e. number of components) of each of these subsets depends on predetermined probabilities of occurrence of different symbol values at different symbol positions in a codeword of the overall codeword set whose symbols have been ordered according to symbol value. The signal components in subsets corresponding to a given memory cell level can then be used to determined the current reference signal level for that cell level. This process is self-adaptive, using read signals from actual 'user cells' (the cells storing encoded user data) to determine reference levels for those cells. Problems associated with use of training data from reference cells are therefore avoided. Moreover, methods embodying the invention combine the universally good performance of the technique of our above-referenced UK patent application with the low latency and low complexity of the technique described in our international patent application. Embodiments of the invention thus offer simple, high-speed decoder implementation with good estimation performance even for very small data records. With these combined qualities, use of MLC memory in main/hybrid memory applications, with significant resulting benefit to the memory hierarchy, becomes eminently feasible.

"The N symbols of each codeword may comprise modulation-coded user data or simply user data expressed in a q.sup.ary alphabet and not otherwise subject to encoding. The overall codeword set comprises the set of such codewords employed in operation of the system.

"A said ordered component set is preferably produced for each of the N component positions of an ordered read signal. Each of these can then be partitioned into up to q subsets each of which corresponds to a respective one of the q memory cell levels. The reference signal level for each of the q memory cell levels can then be determined based on the signal components in the resulting subsets corresponding to that memory cell level. Alternative embodiments can be envisaged, however, as will be discussed further below.

"The reference signal level corresponding to a respective memory cell level may be determined by calculating an average value of the signal components in the subsets corresponding to that memory cell level. The average value here is preferably a mean value.

"The reference signal levels determined from the read signals for a group of stored codewords can then be used to detect those codewords from the read signals. Thus, an embodiment of a second aspect of the invention provides a method for detecting N-symbol codewords of a predefined codeword set, the symbols of each codeword, each of which has one of q symbol values, being stored in respective q-level memory cells, where q>2. The method comprises:

"performing a method according to the first aspect of the invention to determine reference signal levels for respective memory cell levels from the read signals for a group of codewords; and

"detecting the codeword corresponding to each of said read signals in dependence on said reference signal levels.

"An embodiment of a third aspect of the invention provides apparatus for determining reference signal levels corresponding to respective levels of q-level memory cells, the cells storing respective symbols, each of which has one of q symbol values, of N-symbol codewords of a predefined codeword set, where q>2. The apparatus comprises a memory controller for reading the memory cells storing a group of codewords to obtain respective read signals each comprising N signal components corresponding to respective symbols of a codeword, and a level estimator comprising control logic adapted to:

"order the components of each read signal according to signal level to produce an ordered read signal;

"order correspondingly-positioned components of the ordered read signals according to signal level to produce ordered component sets for respective component positions in a said ordered read signal;

"partition each ordered component set into subsets corresponding to respective memory cell levels, wherein the subsets of the ordered component sets contain respective numbers of components dependent on predefined probabilities of occurrence of different symbol values at different positions in a said codeword whose symbols are ordered according to symbol value; and

"determine the reference signal level corresponding to a respective memory cell level in dependence on the signal components in the subsets corresponding to that memory cell level.

"An embodiment of a fourth aspect of the invention provides a data storage device comprising:

"memory having q-level memory cells, where q>2;

"write apparatus for writing in the memory N-symbol codewords of a predefined codeword set, the symbols of each codeword, each of which has one of q symbol values, being stored in respective memory cells; and

"read apparatus comprising apparatus according to the third aspect of the invention for determining reference signal levels for respective memory cell levels from said read signals for a group of codewords, and a codeword detector for detecting the codeword corresponding to each of said read signals in dependence on said reference signal levels.

"In general, where features are described herein with reference to a method embodying the invention, corresponding features may be provided in apparatus embodying the invention, and vice versa.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

"Preferred embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which:

"FIG. 1 is a schematic block diagram of a data storage device embodying the invention;

"FIG. 2 indicates key steps of a level estimation process in the FIG. 1 device;

"FIGS. 3a and 3b illustrate respective ordering steps of the FIG. 2 process;

"FIG. 4 illustrates partitioning of ordered component sets in the FIG. 2 process;

"FIG. 5 indicates construction of an exemplary code for use in the FIG. 1 device;

"FIG. 6 compares performance of the level estimation process of FIG. 2 with two previously-proposed techniques;

"FIG. 7 compares performance of the level estimation process of FIG. 2 with a previously-proposed technique; and

"FIG. 8 indicates complexity reductions obtained with the FIG. 2 process."

URL and more information on this patent application, see: Mittelholzer, Thomas; Papandreou, Nikolaos; Pozidis, Charalampos. Level-Estimation in Multi-Level Cell Memory. Filed January 27, 2014 and posted August 7, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4108&p=83&f=G&l=50&d=PG01&S1=20140731.PD.&OS=PD/20140731&RS=PD/20140731

Keywords for this news article include: Information Technology, Information and Data Storage, International Business Machines Corporation.

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Source: Information Technology Newsweekly


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