News Column

Researchers Submit Patent Application, "Video-Frame Data Receiver with Low Frame Capture Rate", for Approval

August 20, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor Hengstler, Stephan (Campbell, CA), filed on March 31, 2014, was made available online on August 7, 2014.

The patent's assignee is Alverix, Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Assay test kits currently are available for testing a wide variety of medical and environmental conditions or compounds, such as a hormone, a metabolite, a toxin, or a pathogen-derived antigen. Most commonly these tests are used for medical diagnostics either for home testing, point of care testing, or laboratory use. For example, lateral flow tests are a form of immunoassay in which the test sample flows along a solid substrate via capillary action. Some tests are designed to make a quantitative determination, but in many circumstances all that is required is a positive/negative qualitative indication. Examples of such qualitative assays include blood typing, most types of urinalysis, pregnancy tests, and AIDS tests. For these tests, a visually observable indicator such as the presence of agglutination or a color change is preferred.

"Readers for assays including, for example, lateral flow assays may use a camera for acquisition of images from the assay for subsequent processing and analysis. These readers may require an interface between the camera and a microcontroller that accesses images from the camera for subsequent processing and analysis. Conventional solutions of microcontroller-camera interfaces deploy a FGPA, a CPLD or a FIFO as the glue logic between the microcontroller and camera. The purpose of such glue logic is to stream images into a frame buffer located in its internal or external memory. The microcontroller can then access the image data inside the frame buffer for transmission or further processing."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "The present disclosure provides a video frame data receiver that is capable of image acquisition from a camera or other type of image sensor at low frame rates. Such video frame data receivers may be used to capture images indicative of the progress of diagnostic tests or assays in which slow frame capture rates are sufficient including, for example, lateral flow test strips.

"The present disclosure relates to video frame data receivers that comprise at least one microprocessor; at least one signal receiver; and at least one memory device, wherein the at least one memory device stores instructions which, when executed by the at least one microprocessor, cause the at least one microprocessor to operate with the at least one signal receiver to: receive a first synchronizing signal from an image sensor in signal communication with said at least one microprocessor, said image sensor configured to store data indicative of a video frame, said first synchronizing signal indicating whether the image sensor is storing data indicative of an end of a video frame. In an embodiment, the first synchronizing signal (such as a vsync signal) is active for the duration of a capture of a video frame by an image sensor. That is, by sensing that the first synchronizing signal is active, the In a further embodiment, the instructions cause the at least one microprocessor to operate with the at least one signal receiver to receive a second synchronizing signal from the image sensor, said second synchronizing signal indicating whether the image sensor is storing data indicative of an end of one of a plurality of lines of the video frame. In an embodiment, the second synchronizing signal (such as an hsync signal) is active for the duration of a capture of a line of a video frame by an image sensor. In one embodiment, the instructions also cause the at least one microprocessor to operate with the at least one signal receiver to receive a clock signal from the image sensor, said clock signal indicating whether said image sensor is currently storing valid data indicative of at least a portion of the video frame, at a first point in time, determine whether said first synchronizing signal indicates that the image sensor is storing data indicative of the end of at least the portion of the video frame, at said first point in time, also determine whether said second synchronizing signal indicates that the image sensor is storing data indicative of the end of one of the plurality of lines of the video frame. For example, the microprocessor may determine whether both the first synchronizing signal and the second synchronizing signal are both active at the first point in time. If, at the first point in time, the first synchronizing signal indicates that the image sensor is storing data indicative of the end of the video frame and the second synchronizing signal simultaneously indicates that the image sensor is storing data indicative of the end of one of the plurality of lines of the video frame (that is, the synchronizing signals are each active, indicating that the end of a last line of a video frame has been captured), the instructions cause the microprocessor to operate with the at least one signal receiver to poll the clock signal until said clock signal indicates that said image sensor is currently storing valid data indicative of at least a portion of the video frame, and when the clock signal indicates that the image sensor is currently storing valid data indicative of at least a portion of the video frame, to read and store the then-stored data indicative of at least the portion of the video frame from the image sensor.

"In an embodiment, the image sensor operates asynchronously with respect to the at least one microprocessor. For example, the image sensor may operate asynchronously with respect to the at least one microprocessor because the image sensor is in signal communication with an external oscillator. In another embodiment, the image sensor operates asynchronously with respect to the at least one microprocessor due to an external crystal. In an embodiment, the image sensor operates synchronously with respect to the at least one microprocessor by utilizing a same clock signal generator as the at least one microprocessor.

"In an embodiment, the same clock signal generator is a frequency-division circuit which is in signal communication with the at least one microprocessor and the image sensor. In further embodiments, the frequency-division circuit is realized by or implemented as a pulse-width modulator or a programmable clock peripheral.

"In an embodiment, the instructions cause the at least one microprocessor to poll the clock signal until said clock signal indicates that said image sensor is currently storing valid data indicative of at least a portion of the video frame by polling the clock signal until detecting at least one selected from the group consisting of a rising edge of said clock signal and falling edge of said clock signal.

"In an embodiment, the video frame data receiver of the present disclosure further comprises a general purpose input/output peripheral, and the instructions cause the at least one microprocessor to operate with the general purpose input/output peripheral to read and store the then-stored data indicative of at least the portion of the video frame from the image sensor.

"In an embodiment, the video frame data receiver of the present disclosure further comprises an external memory interface, and the instructions cause the at least one microprocessor to operate with the external memory interface to read and store the then-stored data indicative of at least the portion of the video frame from the image sensor. In an embodiment, the external memory interface is a separate package from the printed circuit board containing the microprocessor. In another embodiment, the external memory interface is included in a same package or on a same printed circuit board as the microprocessor--for example, the external memory interface may include an interface to on-chip memory. In certain embodiments, the external memory stores microprocessor instructions for execution by the at least one microprocessor in addition to (or instead of) storing the video frame data from the image sensor.

"In an embodiment, the external memory interface enables the at least one microprocessor to communicate with at least one type of external memory unit selected from the group consisting of: a read only memory (ROM) unit, a flash memory unit, and a static random access memory (SRAM) unit. In one embodiment, wherein the external memory interface enables the at least one microprocessor to communicate with an external read only memory (ROM) unit, it should be appreciated that the external ROM unit may not be configured to store data indicative of at least a portion of a video frame. Rather, the external ROM unit may store only instructions for execution by the at least one microprocessor.

"The present disclosure also relates to or provides video frame data receivers that comprise at least one microprocessor; at least one signal receiver; and at least one memory device, wherein the at least one memory device stores instructions which, when executed by the at least one microprocessor, cause the at least one microprocessor to operate with the at least one signal receiver to: receive a first synchronizing signal from an image sensor, such as a camera, in signal communication with said at least one microprocessor, said image sensor configured to store data indicative of a video frame, said first synchronizing signal indicating whether the image sensor is storing data indicative of an end of a video frame. In an embodiment, the first synchronizing signal (such as a vsync signal) is active for the duration of a capture of a video frame by an image sensor. In a further embodiment, the instructions cause the at least one microprocessor to operate with the at least one signal receiver to receive a second synchronizing signal from the image sensor, said second synchronizing signal indicating whether the image sensor is storing data indicative of an end of one of a plurality of lines of the video frame. In an embodiment, the second synchronizing signal (such as an hsync signal) is active for the duration of a capture of a line of a video frame by an image sensor. In one embodiment, the instructions also cause the at least one microprocessor to operate with the at least one signal receiver to receive a clock signal from the image sensor, said clock signal indicating whether said image sensor is currently storing valid data indicative of at least a portion of the video frame, detect an interrupt based on said clock signal, said interrupt indicating that said image sensor is currently storing valid data indicative of at least a portion of the video frame, upon detection of said interrupt, determine whether said first synchronizing signal indicates that the image sensor is storing data indicative of the end of the video frame and determine whether said second synchronizing signal indicates that the image sensor is storing data indicative of the end of one of the plurality of lines of the video frame. If, upon detection of the interrupt, the first synchronizing signal indicates that the image sensor is storing data indicative of the end of the video frame and the second synchronizing signal indicates that the image sensor is storing data indicative of the end of one of the plurality of lines of the video frame (that is, the synchronizing signals together indicate that the end of a last line of a video frame has been captured), the instructions cause the microprocessor to operate with the at least one signal receiver to read and store the then-stored data indicative of the video frame from the image sensor.

"In an embodiment, the image sensor operates asynchronously with respect to the at least one microprocessor. For example, the image sensor may operate asynchronously with respect to the at least one microprocessor because the image sensor is in signal communication with an external oscillator. Alternatively, the image sensor operates asynchronously with respect to the at least one microprocessor due to the presence of an external crystal.

"In an embodiment, the image sensor operates synchronously with respect to the at least one microprocessor by utilizing a same clock signal generator as the at least one microprocessor. In a further embodiment, the same clock signal generator is frequency-division circuit in signal communication with the at least one microprocessor and the image sensor. In further embodiments, the frequency-division circuit is realized by or implemented as a pulse-width modulator or a programmable clock peripheral which is in signal communication with the at least one microprocessor and the image sensor.

"In an embodiment, the instructions cause the at least one microprocessor to detect an interrupt based on said clock signal by determining at least one selected from the group consisting of a rising edge and a falling edge of said clock signal.

"In an embodiment, the video frame data receiver of the present disclosure further comprises a general purpose input/output peripheral, and wherein the instructions cause the at least one microprocessor to operate with the general purpose input/output peripheral to read and store the then-stored data indicative of at least the portion of the video frame from the image sensor.

"In an embodiment, the video frame data receiver of the present disclosure further comprises an external memory interface, and wherein the instructions cause the at least one microprocessor to operate with the external memory interface to read and store the then-stored data indicative of either or both of at least the portion of the video frame from the image sensor or instructions for execution by the at least one microprocessor. In one embodiment, the external memory interface is a separate package from the printed circuit board containing the microprocessor. In another embodiment, the external memory interface is included in a same package or on a same printed circuit board as the microprocessor--for example, the external memory interface may include an interface to on-chip memory. In certain embodiments, the external memory stores microprocessor instructions for execution by the at least one microprocessor in addition to (or instead of) storing the video frame data from the image sensor.

"In an embodiment, the external memory interface enables the at least one microprocessor to communicate with at least one type of external memory unit selected from the group consisting of: a read only memory (ROM) unit, a flash memory unit, and a static random access memory (SRAM) unit, as discussed above. In one embodiment, wherein the external memory interface enables the at least one microprocessor to communicate with an external read only memory (ROM) unit, it should be appreciated that the external ROM unit may not be configured to store data indicative of at least a portion of a video frame. Rather, the external ROM unit may store only instructions for execution by the at least one microprocessor.

"The present disclosure also provides a video frame data receiver that comprises at least one microprocessor; at least one signal receiver; and at least one memory device, wherein the at least one memory device stores instructions which, when executed by the at least one microprocessor, cause the at least one microprocessor to operate with the at least one signal receiver to: receive a first synchronizing signal from the image sensor, said first synchronizing signal indicating whether the image sensor is storing data indicative of an end of one of a plurality of lines of the video frame. In an embodiment, the first synchronizing signal (such as an hsync signal) is active for the duration of a capture of a line of a video frame by an image sensor. In one embodiment, the instructions also cause the at least one microprocessor to operate with the at least one signal receiver to receive a clock signal from the image sensor, said clock signal indicating whether said image sensor is currently storing valid data indicative of at least a portion of the video frame, detect an interrupt based on said first synchronizing signal, said interrupt indicating that said image sensor is storing data indicative of the end of one of the plurality of lines of the video frame, and upon detection of said interrupt: determine whether the image sensor is currently storing valid data indicative of at least the portion of the video frame (that is, determine whether the first synchronizing signal indicates the end of a last line of a video frame has been captured). If so, the instructions cause the microprocessor to operate with the at least one signal receiver to read and store the then-stored data indicative of at least the portion of the video frame from the image sensor.

"In an embodiment, the image sensor operates asynchronously with respect to the at least one microprocessor because the image sensor is in signal communication with an external oscillator.

"In an embodiment, the image sensor operates synchronously with respect to the at least one microprocessor by utilizing a same clock signal generator as the at least one microprocessor. In one such embodiment, the same clock signal generator is a frequency-division circuit which is in signal communication with the at least one microprocessor and the image sensor. In further embodiments, the frequency-division circuit is realized by or implemented as a pulse-width modulator or a programmable clock peripheral in signal communication with the at least one microprocessor and the image sensor.

"In an embodiment, the instructions cause the at least one microprocessor to detect an interrupt based on said first synchronizing signal by detecting at least one feature of the first synchronizing signal. For example, the microprocessor may detect an interrupt by detecting a rising edge of said first synchronizing signal or a falling edge of said first synchronizing signal.

"In an embodiment, the video frame data receiver of the present disclosure further comprises a general purpose input/output peripheral, and wherein the instructions cause the at least one microprocessor to operate with the general purpose input/output peripheral to read and store the then-stored data indicative of at least the portion of the video frame from the image sensor.

"In an embodiment, the instructions cause the at least one microprocessor to determine whether the image sensor is currently storing valid data indicative of at least the portion of the video frame by polling the clock signal to determine a feature of the clock signal. For example, the microprocessor may poll the clock signal to determine a data-valid edge of said clock signal. In various embodiments, the data-valid edge of the clock signal is either a rising edge of said clock signal or a falling edge of said clock signal. In an embodiment, the instructions cause the at least one microprocessor to determine whether the image sensor is currently storing valid data indicative of the video frame based on whether the clock signal is currently in a data-valid half-period.

"In an embodiment, upon determining that the image sensor is currently storing valid data indicative of the video frame (such as by detecting a rising edge of the clock signal or a falling edge of the clock signal), the instructions cause the at least one microprocessor to read and store the then-stored data indicative of the video frame from the image sensor within a time period equal to less than one-half of the period of the clock signal. In another embodiment, the instructions cause the at least one microprocessor to read the data indicative of the video frame within a time period equal to less than one-half of the period of the clock signal, but storage of that data occurs within a time period exceeding one-half of the period of the clock signal. For example, the disclosed system may read and store the data within an entire clock period. It should be appreciated that any suitable timing for reading and storing may be used in various embodiments.

"In an embodiment, if the image sensor is currently storing valid data indicative of the video frame, the instructions cause the at least one microprocessor to read the then-stored data indicative of the video frame only during the current data-valid half-period. The microprocessor may store the data indicative of the portion of the video frame during a period outside of the data-valid half period. For example, the at least one microprocessor may both read and store the then-stored data indicative of the video frame during an entire clock period.

"The present disclosure also provides video frame data receivers that comprise at least one microprocessor; at least one signal receiver; and at least one memory device, wherein the at least one memory device stores instructions which, when executed by the at least one microprocessor, cause the at least one microprocessor to operate with the at least one signal receiver to: receive a first synchronizing signal from the image sensor, said first synchronizing signal indicating whether the image sensor is storing data indicative of an end of one of a plurality of lines of the video frame. For example, the first synchronizing signal may be a hsync signal as discussed above. In one embodiment, the microprocessor is also programmed to receive a clock signal from the image sensor, said clock signal indicating whether said image sensor is currently storing valid data indicative of at least a portion of the video frame. In one embodiment, the microprocessor detects an interrupt based on said first synchronizing signal, said interrupt indicating that said image sensor is storing data indicative of the end of one of the plurality of lines of the video frame, and upon detection of said interrupt, reads and stores the then-stored data indicative of at least the portion of the video frame from the image sensor only during the current data-valid half-period due to an alignment of said execution of said instructions with said clock signal. In a further embodiment, the microprocessor reads the data indicative of the portion of the video frame during the data-valid half period, and stores the data during a longer period, such as an entire clock period.

"The present disclosure also provides a diagnostic test reader comprising an image sensor for capturing an image of a diagnostic test, said image indicating an outcome of the diagnostic test. In one embodiment, said diagnostic test is an assay test strip. In such an embodiment, the image may indicate the outcome of the diagnostic test by indicating an amount of lateral flow of an assay along said assay test strip. In one embodiment, the diagnostic test reader includes at least one microprocessor; at least one signal receiver; and at least one memory device, wherein the at least one memory device stores instructions which, when executed by the at least one microprocessor, cause the at least one microprocessor to operate with the at least one signal receiver and the at least one image sensor to: receive a first synchronizing signal (such as the hsync signals discussed above) from an image sensor in signal communication with said at least one microprocessor, said image sensor configured to store data indicative of a video frame representing said image, said first synchronizing signal indicating whether the image sensor is storing data indicative of an end of one of a plurality of lines of a video frame representing said image. The microprocessor is additionally configured to receive a clock signal from the image sensor, said clock signal indicating whether said image sensor is currently storing valid data indicative of at least a portion of the video frame. For example, the detecting a feature of the clock signal (such as rising or falling edge of the clock signal) may indicate that the image sensor is currently storing valid data. The microprocessor is also configured to detect an interrupt based on said first synchronizing signal, said interrupt indicating that said image sensor is storing data indicative of the end of one of the plurality of lines of the video frame, and upon detection of said interrupt: determine whether the image sensor is currently storing valid data indicative of at least the portion of the video frame (such as based on the clock signal). If the microprocessor determines that the image sensor is currently storing valid data indicative of at least the portion of the video frame, the microprocessor is configured to read and store the then-stored data indicative of at least the portion of the video frame from the image sensor.

"In an embodiment, upon determining that the image sensor is currently storing valid data indicative of the video frame, the instructions cause the at least one microprocessor to read and store the then-stored data indicative of the video frame from the image sensor within a time period equal to less than one-half of the period of the clock signal. In a further embodiment, the microprocessor does not need to store the data indicative of at least a portion of the video frame within one-half of a clock period. In this embodiment, the microprocessor can read the data indicative of at least a portion of the video frame within the one-half clock period, and can read and store the data within a full clock period. In another embodiment, the microprocessor is programmed to both read and store the data indicative of at least the portion of the video frame within one-half of a clock period.

"Additional features and advantages are described herein, and will be apparent from, the following Detailed Description.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 shows a block diagram of the microcontroller-camera interface.

"FIG. 2 is a flow diagram illustrating the steps performed by a microcontroller in one embodiment of the system disclosed herein."

For additional information on this patent application, see: Hengstler, Stephan. Video-Frame Data Receiver with Low Frame Capture Rate. Filed March 31, 2014 and posted August 7, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4703&p=95&f=G&l=50&d=PG01&S1=20140731.PD.&OS=PD/20140731&RS=PD/20140731

Keywords for this news article include: Electronics, Alverix Inc., Circuit Board, Microcontroller, Microprocessors, Random Access Memory.

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