News Column

Researchers Submit Patent Application, "Semiconductor Device Including Substrate Contact and Related Method", for Approval

August 20, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Nummy, Karen A. (Newburgh, NY); Todi, Ravi M. (Poughkeepsie, NY), filed on January 25, 2013, was made available online on August 7, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "In semiconductor devices, contacts (e.g., substrate contacts, low resistance contacts, contacts to an N+ buried plate, etc.) are frequently included in device design to perform various functions and features of/in the finished device. Formation of these contacts frequently requires inclusion of a number of steps in the semiconductor manufacturing/fabrication process. These steps include etching portions of the semiconductor device to go through formed layers and expose the substrate and/or using a device contact level silicide and/or a (MOL) metal to connect to the N+ buried plate. These processes require a hole to be formed/etched through layers of the semiconductor device and the contact to be positioned within the hole formed in the existing structure. However, in some semiconductor devices (e.g., newer designs, new technologies, smaller design and/or build devices, etc.), etching these holes/contacts and creating a low resistance contact may be problematic due to process integration adjustments and requirements. Further, this etching and formation may create structures on the wafers which are problematic for an integrated process flow (e.g., a non-planar contact structure, deep hole on the wafer, etc.)."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "A first aspect of the disclosure provides a method including: forming a mask on the semiconductor device, the mask exposing at least one contact region including a trench disposed in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact region within the trench; removing a set of node films disposed above the exposed contact region and on the sides of the trench; and forming a contact within the trench to the substrate.

"A second aspect of the disclosure provides a method of forming a contact on a semiconductor device, the method comprising: forming a mask on the semiconductor device, the semiconductor device including a set of contact nodes and the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the at least one exposed contact node within the trench; removing the mask from the semiconductor device; performing a second substrate contact etch on the semiconductor device, the second substrate contact etch recessing the set of contact nodes within the semiconductor device; removing a set of node films disposed above the set of contact nodes and on the sides of the trench; and forming a contact region within the trench above the contact nodes.

"A third aspect of the disclosure provides a method of forming a semiconductor device, the method including: method of forming a contact on a semiconductor device, the method comprising: masking regions of the semiconductor device other than a set of substrate contacts, the set of substrate contacts including a set of contact nodes disposed within a trench in a substrate of the semiconductor device; etching about the set of substrate contacts on the semiconductor device; removing a portion of the set of contact nodes from the trench; and forming a contact region within the trench above the set of contact nodes, the contact region substantially connected to the set of contact nodes and the substrate.

"These and other aspects, advantages and salient features of the invention will become apparent from the following detailed description, which, when taken in conjunction with the annexed drawings, where like parts are designated by like reference characters throughout the drawings, disclose embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other aspects, features and advantages of the invention will be better understood by reading the following more particular description of the invention in conjunction with the accompanying drawings.

"FIG. 1 is a demonstrative illustration of a portion of a semiconductor device according to an embodiment of the invention.

"FIGS. 2-7 are demonstrative illustrations of a method of forming a semiconductor device according to embodiments of the invention.

"FIG. 8 shows a demonstrative illustration of a method flow diagram illustrating steps in a method of forming an integrated circuit (IC) in accordance with an embodiment.

"It is noted that the demonstrative illustrations of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. It is understood that elements similarly numbered between the FIGURES may be substantially similar as described with reference to one another. Further, in embodiments shown and described with reference to FIGS. 1-8, like numbering may represent like elements. Redundant explanation of these elements has been omitted for clarity. Finally, it is understood that the components of FIGS. 1-8 and their accompanying descriptions may be applied to any embodiment described herein."

For additional information on this patent application, see: Nummy, Karen A.; Todi, Ravi M. Semiconductor Device Including Substrate Contact and Related Method. Filed January 25, 2013 and posted August 7, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2620&p=53&f=G&l=50&d=PG01&S1=20140731.PD.&OS=PD/20140731&RS=PD/20140731

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters