No assignee for this patent application has been made.
News editors obtained the following quote from the background information supplied by the inventors: "ADCs are core circuits in a vast array of electronic devices. Low power ADC design is special importance for applications with low-power, high accuracy constraints.
"The power consumption of a conventional analog-to-digital converter (ADC) increases rapidly as a function of its accuracy. Since accuracy is desirable while power consumption is not, current ADC solutions are faced with a trade-off of either spending more power to get a higher accuracy, or by accepting a lower accuracy with a smaller power budget.
"To address this limitation, some researchers have proposed ADC designs with lower power. Nevertheless, more efficient solutions are needed that provide an ADC that has less power consumption for the same accuracy (or, equivalently, more accuracy for the same power consumption) as prior art designs."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "The present invention provides, in one aspect, SAR ADCs with improved accuracy and power-efficiency. Inside low-power successive approximation (SAR) ADCs, the comparator becomes dominant for the overall power when considering higher resolutions. The comparator decides a set of digital output bits that describes the analog input signal. In high-resolution (i.e., greater than 10-bit) ADCs the power consumption is driven by thermal noise constraints (every 6 dB increase in resolution comes at the cost of a 4-fold increase in power consumption). To overcome this fundamental scaling rule, the inventor discovered a Data-Driven Noise-Reduction technique (DDNR) to efficiently suppress comparator noise by means of selective noise enhancement. More specifically, in addition to determining the bits themselves, there is circuitry to determine the reliability of each individual bit being converted. Based on the reliability, a decision logic for each bit-decision either keeps the bit as it is (if the bit appears to be reliable enough), or activates a noise reduction scheme that enhances the reliability of this individual bit (if the bit is not reliable enough). In one embodiment, the noise-reduction scheme repeats the same comparator operation multiple times and uses majority-voting to decide the final output, thereby improving the reliability of the determined bit. Alternatively, other noise-reduction schemes such as oversampling, noise-shaping or sigma-delta modulation may be used instead. Advantageously, because it is implemented in the digital domain, the noise-reduction scheme can be reconfigured by hardware or software, dynamically and/or adaptively, to adjust the amount of noise-reduction. In this way, a flexible trade-off between power and accuracy can be made after production of the ADC. Advantageously, the noise reduction scheme is selective (i.e., only applied for unreliable bit conversions), so it is much more power efficient compared to traditional unselective methods.
"The level of performance achievable by embodiments of this invention exceeds state-of-the-art-implementations by providing both higher accuracy and lower power consumption. The best prior-art design has achieved performance of 2.8fJ/conversion-step. Embodiments of the present invention, in contrast, provide an achieved performance of 2.2fJ/conversion-step, which represents almost 25% power reduction. At the same time, an accuracy improvement of 5 dB is achieved.
"In one aspect, the invention provides a successive operation register (SAR) analog-to-digital converter (ADC) circuit that includes a voltage comparator having a first analog signal input, a second analog input, and a decision output; a decision logic circuit having an input connected to the decision output of the voltage comparator and a digital output; a digital-to-analog converter (DAC) having a digital input connected to the digital output of the decision logic circuit and an analog output connected to the second analog input of the voltage comparator. The ADC circuit further includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time .tau..sub.MV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time .tau..sub.MV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator.
"In a differential implementation, the digital-to-analog converter (DAC) may also have a second analog output connected to the first analog input of the voltage comparator.
"The digital noise reduction circuit may use a multiple voting logic to produce a majority vote value as the noise-reduced decision output, and may further include an oscillation circuit that generates a variable over-sampled clock signal for the multiple voting logic. The digital noise reduction circuit may be configurable in a number of repeated votes (Nv) per bit decision used in the voting logic and a number of voting cycles (Nc) per conversion used in the voting logic, and the ADC may include a feedback circuit that controls .tau..sub.MV of the bit reliability circuit based in part on the number of voting cycles (Nc) per conversion.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIGS. 1A and 1B are graphs of comparator output probabilities (P.sub.0 and P.sub.1) and error probability (P.sub.e), respectively, with respect to the ratio of signal input to comparator noise, according to an embodiment of the invention.
"FIG. 2 show graphs of the error probability of an initial comparator (P.sub.e), after 4 times analog scaling (P.sub.e,4x) and after 5 times majority voting (P.sub.e,5v) with respect to the ratio of signal input to comparator noise, according to an embodiment of the invention. Also shown are transistor-level transient-noise simulation error probabilities of a comparator without voting and after 5 times voting.
"FIG. 3 is a graph of relative equivalent comparator noise as a function of the number of samples in the voting scheme, comparing a theoretical model and transistor-level transient-noise simulations, according to an embodiment of the invention.
"FIG. 4 is a timing diagram of a 12 bit SAR conversion with Data-Driven Noise Reduction (DDNR) according to an embodiment of the invention.
"FIGS. 5A and 5B are graphs of simulated ADC input-referred noise and number of extra comparisons, respectively, versus majority-voting threshold for various amounts of comparator noise (.sigma..sub.noise.alpha. LSB), according to an embodiment of the invention.
"FIG. 6 is a circuit diagram illustrating a
"FIGS. 7A and 7B are circuit diagrams illustrating a segmented charge-redistribution DAC, according to an embodiment of the invention.
"FIGS. 8A and 8B are circuit diagrams illustrating a comparator implementation with 'Comparison Ready'-output (RDY), according to an embodiment of the invention.
"FIG. 9 is a timing diagram illustrating bit-cycling clock generation, according to an embodiment of the invention.
"FIG. 10 is a circuit diagram illustrating a self-oscillation circuit that can be applied around the comparator, according to an embodiment of the invention.
"FIG. 11 is a timing diagram illustrating a simulation of the self-oscillating comparator at 0.6 V supply, according to an embodiment of the invention.
"FIG. 12 is a circuit diagram illustrating an implementation of a Data-Driven Noise-Reduction method, according to an embodiment of the invention.
"FIG. 13 is a circuit diagram illustrating an implementation of an adaptive Data-Driven Noise-Reduction method, according to an embodiment of the invention."
For additional information on this patent application, see: Harpe,
Keywords for this news article include: Patents, Electronics, Digital To Analog.
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