News Column

Patent Issued for Using a Single Mask for Various Design Configurations

August 20, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Landis, Lawrence David (Pleasanton, CA); Price, Richard (San Jose, CA), filed on January 13, 2009, was published online on August 5, 2014.

The assignee for this patent, patent number 8796740, is Altera Corporation (San Jose, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "Integrated circuits are usually fabricated on a semiconductor wafer. During the manufacturing process, a stepper machine is used to move the processing arm to print images, i.e. dies, on a wafer. The pattern on the photomask (also called a reticle) is exposed repeatedly side by side on the surface of the wafer. Multiple dies are usually formed on the surface of a single wafer. Depending on the size of the die, in some cases, multiple die patterns can be included on a single reticle to reduce the cost for the reticle set.

"Multiple layers of these reticle images make up a device. Normally, each different layer will be formed by a different reticle, and as the number of layers in a device increases with each technology node, the mask set cost to produce a device increases. Furthermore, in order to produce a different device, e.g., a device of a different size or a device with more resources, a new reticle set would normally be required, further increasing the mask cost. In order to reduce the cost of a device, the number of masks required to produce a single device needs to be reduced. The cost of the device can then be lowered by maximizing the reusability of a single mask set and a more cost effective solution can be achieved by sharing mask sets for multiple devices.

"It would therefore be advantageous if a single mask set can be used to handle a variety of design sizes with varying resources. In other words, the same mask set can be used to create a number of different devices with different configurations."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Embodiments of the present invention provide various techniques that allow a single mask set to be used for designing and manufacturing semiconductor devices or integrated circuits of various sizes. The invention utilizes a single mask set that can handle a variety of devices of different sizes without creating a new mask set for each different device.

"It should be appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.

"In one embodiment, a wafer with a plurality of tiles is disclosed. Each tile has a number of fixed resource blocks which include, among other things, memory blocks, I/O banks, transceivers, and auxiliary circuits. Each of the tiles also has a plurality of logic blocks which include logic cells and gates used for implementing the intended logic function. A scribe region surrounds each individual tile. In one embodiment, the scribe region is used for sawing the tile from the wafer. Each tile can be configured to connect to one or more adjacent tiles through interconnect lines that connect the resource blocks and logic blocks in one tile to the resource blocks and logic blocks in another tile.

"In another embodiment, another wafer is disclosed. The wafer has a plurality of tiles. Each tile has multiple resource blocks and a customizable die seal surrounding the resource blocks in the tile. The die seal can be customized to connect each of the tiles to an adjacent tile. A scribe region surrounds an outer boundary of the die seal of each of the tiles. The wafer has a plurality of dies formed from the tiles on the wafer. Each die can be formed by either a single tile or multiple tiles connected together. In one embodiment, the die seal has an opening to route interconnect lines to connect one tile to one or more adjacent tiles.

"In yet another embodiment in accordance with the present invention, a method of manufacturing an integrated circuit (IC) is disclosed. The method includes creating multiple tile patterns on a wafer. Each of the tile patterns has numerous fixed resources. A die seal with an opening is created. The die seal surrounds the fixed resources in each of the tile patterns. Two or more adjacent tile patterns on the wafer are connected through the opening in the die seal. The wafer is cut along scribe lines on the wafer. Numerous ICs are formed by cutting the wafer along the scribe lines to separate the multiple tile patterns on the wafer.

"Other aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention."

For more information, see this patent: Landis, Lawrence David; Price, Richard. Using a Single Mask for Various Design Configurations. U.S. Patent Number 8796740, filed January 13, 2009, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8796740.PN.&OS=PN/8796740RS=PN/8796740

Keywords for this news article include: Electronics, Semiconductor, Altera Corporation.

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Source: Electronics Newsweekly


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