News Column

Patent Issued for System on a Chip (SOC) Debug Controllability

August 21, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Gulati, Manu (Saratoga, CA); Ramsay, James D. (San Jose, CA); Machnicki, Erik P. (San Jose, CA); Yu, Jianlin (Cupertino, CA), filed on June 26, 2012, was published online on August 5, 2014.

The assignee for this patent, patent number 8799715, is Apple Inc. (Cupertino, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "This invention is related to the field of integrated circuits such as systems on a chip (SOCs) and, more particularly, to debug features of SOCs.

"As the number of transistors that can be integrated onto a single integrated circuit (IC) 'chip' continues to increase, the amount of functionality and complexity that can be included increases as well. SOCs are one way in which the additional functionality/complexity is employed, by integrating various peripheral functionality onto the IC with one or more processors that are the central processing unit (CPU) of the system. The peripheral functionality can include processors as well (e.g. embedded processors, microcontrollers, digital signal processors, graphics processors, etc.), and can include fixed function circuitry such as peripheral interface controllers, encoders and decoders, graphics processing hardware, audio processing hardware, memory controllers, etc.

"The continued integration of functionality/complexity into an SOC leads to complications for debugging. Both hardware problems and software problems can result in errant or unexpected operation, and typically the system engineer/software engineer needs to analyze various system state to identify the problem and how to fix it or work around it. CPUs generally include various debugging features (e.g. breakpoints on certain instructions or fetch addresses, address monitoring for data accesses, single step instruction execution modes, etc.). The CPU halt features, which are tied to the concept of a centralized, synchronous execution pipeline and execution of instructions, do not naturally extend to other components that have no notion of pipelining or instruction execution, and which run asynchronously with the CPUs and other blocks."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component: different components may support different events based on the functionality implemented in that component. The local debug control units may be programmable to enable events to be detected, and may transmit the detected events to the SOC debug control unit. The SOC debug control unit may be programmable to detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events. The state of the SOC may be observable (e.g. scanned out) and, in some embodiments, controllable (e.g. modified state may be scanned in). An engineer debugging the SOC and/or software executing on the SOC may thus have enhanced visibility and control of the system. In some embodiments, an SOC may not include a CPU complex, but may include the remaining components mentioned above.

"In some embodiments, an event detected in one local debug control unit may be used as a trigger to begin monitoring for another event in another local debug control unit. Additional flexibility in identifying a desired system state at which to halt may thus be realized, in some embodiments. In an embodiment, the SOC debug control unit may support a programmable delay after identifying a specified event or combination of events, prior to halting the SOC. The delay may allow for additional operation to occur, and over multiple executions the state at various points following the event may be determined. Fine granularity debugging may thus be possible in some embodiments. In some embodiments, the state of the SOC may be scanned out, modified, and scanned back in. The modification of the state may allow for testing of bug theories, workarounds, etc."

For more information, see this patent: Gulati, Manu; Ramsay, James D.; Machnicki, Erik P.; Yu, Jianlin. System on a Chip (SOC) Debug Controllability. U.S. Patent Number 8799715, filed June 26, 2012, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8799715.PN.&OS=PN/8799715RS=PN/8799715

Keywords for this news article include: Software, Apple Inc..

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Source: Computer Weekly News


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