News Column

Patent Issued for Semiconductor Package and Fabrication Method

August 20, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Hsiao, Wei Chung (Taichung, TW); Lin, Chun Hsien (Taichung, TW); Pai, Yu Cheng (Taichung, TW); Hung, Liang Yi (Taichung, TW); Sun, Ming Chen (Taichung, TW); Tang, Shao Tzu (Taichung, TW); Tsai, Ying Chou (Taichung, TW); Lan, Chang Yi (Taichung, TW), filed on August 17, 2012, was published online on August 5, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8796867 is assigned to Siliconware Precision Industries Co., Ltd. (Taichung, TW).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to semiconductor packages and fabrication methods thereof, and, more particularly, to a semiconductor package and a fabrication method thereof for improving the product reliability.

"Semiconductor packaging technologies have been continuously improved to meet the miniaturization requirement of electronic products. A semiconductor package generally includes a packaging substrate, a semiconductor chip disposed on the packaging substrate, an encapsulant encapsulating the semiconductor chip, and a plurality of solder balls for an electronic device to be electrically connected thereto. As such, the overall thickness of the semiconductor package includes the thickness of the encapsulant, the thickness of the packaging substrate and the height of the solder balls. Therefore, reducing the thickness of the packaging substrate has become an important factor to reduce the size of the semiconductor package.

"Conventionally, a core layer is formed in the packaging substrate for improving the rigidity of the overall structure, thereby facilitating subsequent chip bonding and encapsulation processes. However, the core layer increases the thickness of the packaging substrate and results in an increased height of the overall package structure.

"Accordingly, coreless packaging substrates are developed to meet the miniaturization requirement. FIGS. 1A to 1C are schematic cross-sectional views showing a fabrication method of a semiconductor package 1 as disclosed by U.S. Pat. No. 7,795,071.

"Referring to FIG. 1A, a coreless packaging substrate la is formed on a carrier (not shown) and then the carrier is removed. The coreless packaging substrate la has an insulating protection layer 14 and a circuit layer 13 embedded in the insulating protection layer 14. A lower surface of the circuit layer 13 is flush with a lower surface of the insulating protection layer 14, and an opposite upper surface of the insulating protection layer 14 has a plurality of openings 140 formed therein for exposing a portion of an upper surface of the circuit layer 13.

"Referring to FIG. 1B, at least a semiconductor chip 17 is disposed on the lower surface of the insulating protection layer 14 and electrically connected to the circuit layer 13 through a plurality of conductive bumps 170.

"Referring to FIG. 1C, a surface finish 12 is formed on the exposed portion of the circuit layer 13 in the openings 140.

"By dispensing with a core layer, the fabrication cost and time of the packaging substrate 1a are reduced. On the other hand, the packaging substrate 1a has reduced rigidity due to its reduced thickness. Therefore, the packaging substrate 1a can easily crack during a subsequent chip bonding or encapsulation process, thereby reducing the product yield and reliability.

"Further, after the carrier is removed, warpage can easily occur to the packaging substrate 1a so as to cause delamination between the circuit layer 13 and the insulating protection layer 14. As such, the packaging substrate 1a must be discarded, thus increasing the material cost.

"Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "In view of the above-described drawbacks, the present invention provides a semiconductor package, which comprises: a packaging substrate having an insulating protection layer and a circuit layer embedded in the insulating protection layer, wherein the circuit layer comprises a first sub-circuit layer, a second sub-circuit layer and a third sub-circuit layer in sequence and has opposite first and second surfaces, the first surface of the circuit layer is exposed from a surface of the insulating protection layer, and an opposite surface of the insulating protection layer has at least an opening formed therein for exposing a portion of the second surface of the circuit layer; a chip disposed on the packaging substrate and electrically connected to the first surface of the circuit layer; and an encapsulant formed on the packaging substrate for encapsulating the chip.

"The present invention further provides a fabrication method of a semiconductor package, which comprises the steps of: forming a circuit layer on a first carrier, wherein the circuit layer has a first surface bonded to the first carrier and a second surface opposite to the first surface; forming an insulating protection layer on the first carrier and the circuit layer and forming at least an opening in the insulating protection layer for exposing a portion of the second surface of the circuit layer; bonding a second carrier to the insulating protection layer; removing the first carrier so as to expose the first surface of the circuit layer and the insulating protection layer; disposing a chip on the insulating protection layer and electrically connecting the chip and the first surface of the circuit layer; forming an encapsulant on the insulating protection layer and the first surface of the circuit layer for encapsulating the chip; and removing the second carrier.

"In an embodiment, the first and second carriers can be made of glass fiber (FR4), glass or metal.

"In an embodiment, the circuit layer can further comprise a first sub-circuit layer, a second sub-circuit layer and a third sub-circuit layer in sequence.

"In an embodiment, the first surface of the circuit layer can be flush with the surface of the insulating protection layer.

"In an embodiment, the insulating protection layer can be made of a solder mask material or a molding compound.

"In an embodiment, a surface finish or a metal layer can be formed on the circuit layer according to the material structure of the circuit layer. For example, if the first sub-circuit layer is made of gold or silver, the second sub-circuit layer is made of nickel and the third sub-circuit layer is made of copper, the surface finish made of gold or silver can be formed on the second surface of the circuit layer. Alternatively, if the first sub-circuit layer is made of gold, the second sub-circuit layer is made of nickel and the third sub-circuit layer is made of palladium, the metal layer can be made of copper and can be formed on the second surface of the circuit layer, and a surface finish can be selectively formed on the metal layer. The surface finish can be made of Sn, Ag, Ni, Pd, Au, solder, lead-free solder, or a combination thereof.

"According to the present invention, the first carrier is used as a support member during the fabrication of the thin-type packaging substrate so as to avoid warpage of the thin-type packaging substrate and hence prevent delamination from occurring between the circuit layer and the insulating protection layer.

"Further, after the second carrier is bonded to the thin-type packaging substrate and the first carrier is removed, the second carrier provides the thin-type packaging substrate with sufficient rigidity for effectively undergoing the chip bonding and encapsulation processes without cracking, thereby greatly improving the product yield and reliability."

URL and more information on this patent, see: Hsiao, Wei Chung; Lin, Chun Hsien; Pai, Yu Cheng; Hung, Liang Yi; Sun, Ming Chen; Tang, Shao Tzu; Tsai, Ying Chou; Lan, Chang Yi. Semiconductor Package and Fabrication Method. U.S. Patent Number 8796867, filed August 17, 2012, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8796867.PN.&OS=PN/8796867RS=PN/8796867

Keywords for this news article include: Electronics, Semiconductor, Microtechnology, Siliconware Precision Industries Co. Ltd.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters