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Patent Issued for Semiconductor Device Including Power-On Reset Circuit

August 20, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Lee, Jung-ho (Goyang, KR); Bae, Hyun-soo (Guri, KR); Oh, Won-hi (Bucheon, KR); Lee, Jong-mu (Seoul, KR), filed on September 27, 2013, was published online on August 5, 2014.

The patent's assignee for patent number 8797071 is Fairchild Korea Semiconductor Ltd. (Bucheon, KR).

News editors obtained the following quote from the background information supplied by the inventors: "The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a power-on reset circuit.

"To enable reliable operations of circuits of a multifunctional device, such as a large-scale integration (LSI) device and a power semiconductor device, initial conditions of the circuits need to be set. A power-on-reset (POR) circuit may function to set the initial conditions of the circuits of the multifunctional device.

"More specifically, during an increase in internal voltage with a rise in power supplied to a chip, the POR circuit detects a specific electric potential of the power and generate a pulse signal (hereinafter, referred to as a 'POR signal'). The POR circuit may be applied to circuit blocks, such as a latch, a flip-flop, and a register, which need to be initialized so that data stored in the circuit blocks can be reset. An ideal POR signal should be stable despite fluctuation of an electric potential due to external noise during a steady-mode operation in power ramp-up."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "The inventive concept provides a semiconductor device including a power-on-reset (POR) circuit that may stably operate even if a power electric potential fluctuates due to noise during a steady-mode operation.

"According to an aspect of the inventive concept, there is provided a semiconductor device including: a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope; and a first power-on-reset (POR) signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time.

"The device may further include a storage unit configured to store data and initialize the stored data by receiving the first POR signal.

"The first POR signal generator may include an asymmetric inverter configured to receive the first voltage, invert the first voltage, and generate an output signal that sharply decreases with a rise of the first voltage.

"The driving voltage generator may include a beta multiplier.

"The driving voltage generator may be further configured to receive a supply voltage rising at a third slope and generate the first voltage. The first slope at which the first voltage rises may be less than the third slope, and the second slope at which the first voltage rises may be greater than the third slope.

"The device may further include: a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof; a capacitive unit connected between the output terminal of the voltage divider and the second power supply source; and a second POR signal generator connected to the output terminal of the voltage divider and configured to receive the second voltage and generate a second POR signal having a second ramp-up time. The first ramp-up time may be longer than the second ramp-up time.

"The device may further include a storage unit configured to store data and initialize the stored data by receiving the first POR signal or the second POR signal.

"The device may further include: a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof; a reference voltage generator configured to generate a reference voltage; and a comparator configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage and generate a third POR signal having a third ramp-up time. The first ramp-up time may be less than the third ramp-up time.

"The device may further include a storage unit configured to store data and initialize the stored data by receiving the first POR signal or the third POR signal.

"The device may further include: a second POR signal generator configured to generate a second POR signal having a second ramp-up time; and an undervoltage-lockout (UVLO) module configured to generate a third POR signal having a third ramp-up time.

"The first ramp-up time may be greater than the second ramp-up time and less than the third ramp-up time.

"The device may further include a storage unit configured to store data and initialize the stored data by receiving at least one of the first through third POR signals.

"The device may further include a voltage divider connected between a first power supply source and a second power supply source. The second POR signal generator and the UVLO module may receive a voltage from the voltage divider and generate the second and third POR signals, respectively.

"The UVLO module may include: a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof; a reference voltage generator configured to generate a reference voltage; and a comparator configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage and generate the third POR signal having the third ramp-time.

"The device may further include a capacitive unit connected between the output terminal of the voltage divider and the second power supply source, and the second POR signal generator may be connected to the output terminal of the voltage divider and configured to receive the second voltage and generate the second POR signal having the second ramp-up time.

"The first ramp-up time may be longer than the second ramp-up time and shorter than the third ramp-up time.

"The device may further include: a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof; a capacitive unit connected between the output terminal of the voltage divider and the second power supply source; a second POR signal generator connected to the output terminal of the voltage divider and configured to receive the second voltage and generate the second POR signal having the second ramp-up time; a reference voltage generator configured to generate a reference voltage; and a comparator configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage and generate the third POR signal having the third ramp-up time.

"The first ramp-up time may be longer than the second ramp-up time and shorter than the third ramp-up time.

"According to another aspect of the inventive concept, there is provided a semiconductor device including: a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope; a first POR signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time; a voltage divider connected between a first power supply source and a second power supply source and configured to provide a second voltage from an output terminal thereof; a capacitive unit connected between the output terminal of the voltage divider and the second power supply source; a second POR signal generator connected to the output terminal of the voltage divider and configured to receive the second voltage and generate a second POR signal having a second ramp-up time; a reference voltage generator configured to generate a reference voltage; a comparator configured to compare the second voltage of the output terminal of the voltage divider with the reference voltage and generate a third POR signal having a third ramp-up time; and a storage unit configured to store data, receive at least one of the first through third POR signals, and initialize the stored data. The first ramp-up time is longer than the second ramp-up time and shorter than the third ramp-up time.

"According to another aspect of the inventive concept, there is provided a semiconductor device including: a voltage divider connected between a first power supply source and a second power supply source and configured to provide a first voltage through an output terminal thereof; a capacitive unit connected between the output terminal of the voltage divider and the second power supply source; a POR signal generator connected to the output terminal of the voltage divider and configured to receive the first voltage and generate a first POR signal having a first ramp-up time; a reference voltage generator configured to generate a reference voltage; and a comparator configured to compare the first voltage of the output terminal of the voltage divider with the reference voltage and generate a second POR signal having a second ramp-up time. The first ramp-up time is shorter than the second ramp-up time."

For additional information on this patent, see: Lee, Jung-ho; Bae, Hyun-soo; Oh, Won-hi; Lee, Jong-mu. Semiconductor Device Including Power-On Reset Circuit. U.S. Patent Number 8797071, filed September 27, 2013, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8797071.PN.&OS=PN/8797071RS=PN/8797071

Keywords for this news article include: Electronics, Fairchild Korea Semiconductor Ltd..

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Source: Electronics Newsweekly


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