News Column

Patent Issued for Semiconductor Device and Manufacturing Method

August 22, 2014



By a News Reporter-Staff News Editor at Health & Medicine Week -- Renesas Electronics Corporation (Kanagawa, JP) has been issued patent number 8796780, according to news reporting originating out of Alexandria, Virginia, by NewsRx editors (see also Lapis Semiconductor Co., Ltd.).

The patent's inventors are Yamamoto, Yoshiki (Tokyo, JP); Nishida, Yukio (Tokyo, JP); Yugami, Jiro (Tokyo, JP).

This patent was filed on October 2, 2009 and was published online on August 5, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, to a semiconductor device equipped with CMOSFET having a high-k/metal gate structure and a manufacturing method of the device.

"In order to improve an integration density and performance of semiconductor devices, miniaturization of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which is a constituent component of the semiconductor devices, has been continuously progressing. With realization of miniaturization, however, an influence of a short-channel effect is increasing. Control of this influence is therefore considered to be important. As a measure against this problem, high-k (high dielectric constant) gate insulating film/metal gate structures are known. In these structures, sufficient thickness of the insulating film enables to decrease a leakage current caused by a quantum tunneling effect and at the same time, use of the high-dielectric-constant insulating film enables to raise the amount of current. In addition, use of a metal gate in combination is effective for suppressing phonon oscillation.

"In the typical gate first process, gates of CMOSFET having high-k/metal gate structures are formed by the following manufacturing process. First, after deposition of either an n type or a p type gate metal, the gate metal is removed by etching from a region having a polarity opposite thereto. Then, a metal having a polarity opposite to that of the metal deposited first is deposited over the metal removed region. A substance (typically, poly-Si or W) for making gates of equal height or equal resistance is deposited, followed by gate etching to form the gates.

"When the typical gate first process as described above is employed, however, a dual metal gate is formed using metals having different work functions for the n type and p type, respectively. This means that materials different in physical and chemical properties should be etched simultaneously, leading to a problem, that is, difficulty in processing.

"As a resolution of this problem, there is known a method of forming a capping layer on the high-k film and controlling the work function by using one gate metal. In this CMOSFET using the capping layer, a gate is obtained by forming a high-k gate insulating film, depositing a capping layer, removing the capping layer from a region of a polarity which does not need the capping layer, depositing a gate metal, depositing poly-Si or W, and then etching.

"The technologies related to the above description are disclosed in the following Patent Documents 1 and 2, and Non-patent Document 1. [Patent Document] U.S. Pat. No. 6,545,324 [Patent Document 2] Japanese Unexamined Patent Publication No. 2007-200946 [Non-patent Document 1] IEDM2007, 'Single Metal/Dual High-k Gate Stack with Low Vth and Precise Gate Profile Control for Highly Manufacturable Aggressively Scaled CMISFETs', Mise, N et. al, pp 527-530"

Supplementing the background information on this patent, NewsRx reporters also obtained the inventors' summary information for this patent: "The semiconductor device using a capping layer does not pose the problem of processability in gate etching, because it uses one kind of a metal and one kind of a high-k insulating film. In a step of removing the capping layer from either an n type region or a p type region, La compounds used ordinarily for the capping layer are so strongly hygroscopic that they cannot be removed easily through a mask. It is therefore difficult to form a capping layer with a good shape and thereby control the work function.

"The invention has been made with a view to overcoming such problems. An object of the invention is to provide a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively; and a manufacturing method of the device.

"A semiconductor device according to one embodiment of the invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first conductivity type MOSFET and the second conductivity type MOSFET are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control the work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of the work-function controlling material into the interface of the first insulating film.

"A semiconductor device according to another embodiment of the invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first conductivity type MOSFET and the second conductivity type MOSFET are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, a cap layer formed over the second insulating film and containing a material which diffuses into the second insulating film to control the work function thereof, and a gate electrode formed over the cap layer and having a metal layer as a lower layer of the gate electrode. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of the work-function controlling material into the interface of the first insulating film.

"A semiconductor device according to a further embodiment of the invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first conductivity type MOSFET and the second conductivity type MOSFET are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control the work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the second insulating film and the metal layer to prevent diffusion of the work-function controlling material into the second insulating film.

"A semiconductor device according to a still further embodiment of the invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first conductivity type MOSFET and the second conductivity type MOSFET are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, a cap layer formed over the second insulating film and containing a material which diffuses into the second insulating film to control the work function thereof, and a gate electrode formed over the cap layer and having, as a lower layer of the gate electrode, a metal layer. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the second insulating film and the cap layer to prevent diffusion of the work-function controlling material into the second insulating film.

"A manufacturing method of a semiconductor device according to one embodiment of the invention is that of a semiconductor device having a first conductivity type MOSFET and a second conductivity type MOSFET. First, a semiconductor substrate having, over the upper surface thereof, a first insulating film is prepared. Then, over the first insulating film, a diffusion barrier film for preventing diffusion of a work-function controlling material into the interface of the first insulating film is formed. The diffusion barrier film is then removed to expose the surface of the first insulating film in a first conductivity type MOSFET formation region. Then, over the first insulating film and the diffusion barrier film, a second insulating film made of an insulating material having a higher dielectric constant than the first insulating film is formed. Over the second insulating film, a gate electrode having, as a lower layer thereof, a metal layer containing a material which diffuses into the second insulating film to control the work function thereof is formed.

"A manufacturing method of a semiconductor device according to another embodiment of the invention is that of a semiconductor device having a first conductivity type MOSFET and a second conductivity type MOSFET. First, a semiconductor substrate having, over the upper surface thereof, a first insulating film is prepared. Then, over the first insulating film, a diffusion barrier film for preventing diffusion of a work-function controlling material into the interface of the first insulating film is formed. The diffusion barrier film is then removed to expose the surface of the first insulating film in a first conductivity type MOSFET formation region. Then, over the first insulating film and the diffusion barrier film, a second insulating film made of an insulating material having a higher dielectric constant than the first insulating film is formed. Over the second insulating film, a cap layer containing a material which diffuses into the second insulating film to control the work function thereof is formed. A gate electrode having, as a lower layer thereof, a metal layer is formed over the cap layer.

"A manufacturing method of a semiconductor device according to a further embodiment of the invention is that of a semiconductor device having a first conductivity type MOSFET and a second conductivity type MOSFET. First, a semiconductor substrate having, over the upper surface thereof, a first insulating film is prepared. Then, over the first insulating film, a second insulating film made of an insulating material having a higher dielectric constant than the first insulating film is formed. Over the second insulating film, a diffusion barrier film for preventing diffusion of a work-function controlling material into the second insulating film is formed. The diffusion barrier film is then removed to expose the surface of the second insulating film in the first conductivity type MOSFET formation region. Then, over the second insulating film and the diffusion barrier film, a gate electrode having, as a lower layer thereof, a metal layer which diffuses into the second insulating film to control the work function thereof is formed.

"A manufacturing method of a semiconductor device according to a still further embodiment of the invention is that of a semiconductor device having a first conductivity type MOSFET and a second conductivity type MOSFET. First, a semiconductor substrate having, over the upper surface thereof, a first insulating film is prepared. Then, over the first insulating film, a second insulating film made of an insulating material having a higher dielectric constant than the first insulating film is formed. Over the second insulating film, a diffusion barrier film for preventing diffusion of a work-function controlling material into the second insulating film is formed. The diffusion barrier film is then removed to expose the surface of the second insulating film in the first conductivity type MOSFET formation region. Then, over the second insulating film and the diffusion barrier film, a cap layer containing a material which diffuses into the second insulating film to control the work function thereof is formed. Over the cap layer, a gate electrode having, as a lower layer thereof, a metal layer is then formed.

"According to the semiconductor device and the manufacturing method thereof in the one embodiment of the invention, the diffusion barrier film is formed between the first insulating film and the second insulating film in the second conductivity type region. Diffusion of the work-function controlling material of the metal layer into the first insulating film/second insulating film interface is thereby prevented in the second conductivity type region, while the work-function controlling material of the metal layer diffuses into the first insulating film/second insulating film interface in the first conductivity type region. As a result, a single metal/dual high-k structure with a good shape can be formed without processing a highly hygroscopic La compound and at the same time, flat band voltages suited for nMOS and pMOS, respectively, can be achieved.

"According to the semiconductor device and the manufacturing method thereof in the another embodiment of the invention, the diffusion barrier film is formed between the first insulating film and the second insulating film in the second conductivity type region. Diffusion of the work-function controlling material of the cap layer into the first insulating film/second insulating film interface is thereby prevented in the second conductivity type region, while the work-function controlling material of the cap layer diffuses into the first insulating film/second insulating film interface in the first conductivity type region. As a result, a single metal/dual high-k structure with a good shape can be formed without processing a highly hygroscopic La compound and at the same time, flat band voltages suited for nMOS and pMOS, respectively, can be achieved.

"According to the semiconductor device and the manufacturing method thereof in the further embodiment of the invention, the diffusion barrier film is formed between the second insulating film and the metal layer in the second conductivity type region. Diffusion of the work-function controlling material of the metal layer into the second insulating film is thereby prevented in the second conductivity type region, while the work-function controlling material of the metal layer diffuses into the first insulating film/second insulating film interface in the first conductivity type region. As a result, a single metal/dual high-k structure with a good shape can be formed without processing a highly hygroscopic La compound and at the same time, flat band voltages suited for nMOS and pMOS, respectively, can be achieved.

"According to the semiconductor device and the manufacturing method thereof in the still further embodiment of the invention, the diffusion barrier film is formed between the second insulating film and the cap layer in the second conductivity type region. Diffusion of the work-function controlling material of the cap layer into the second insulating film is thereby prevented in the second conductivity type region, while the work-function controlling material of the cap layer diffuses into the first insulating film/second insulating film interface in the first conductivity type region. As a result, a single metal/dual high-k structure with a good shape can be formed without processing a highly hygroscopic La compound and at the same time, flat band voltages suited for nMOS and pMOS, respectively, can be achieved."

For the URL and additional information on this patent, see: Yamamoto, Yoshiki; Nishida, Yukio; Yugami, Jiro. Semiconductor Device and Manufacturing Method. U.S. Patent Number 8796780, filed October 2, 2009, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8796780.PN.&OS=PN/8796780RS=PN/8796780

Keywords for this news article include: Electronics, Microtechnology, Renesas Electronics Corporation, Semiconductor.

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Source: Health & Medicine Week


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