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Patent Issued for Optimization Metallization for Prevention of Dielectric Cracking under Controlled Collapse Chip Connections

August 20, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Bonilla, Griselda (Fishkill, NY); Daubenspeck, Timothy H. (Colchester, VT); Lamorey, Mark C. H. (South Burlington, VT); Landis, Howard S. (Underhill, VT); Liu, Xiao Hu (Briarcliff Manor, NY); Questad, David L. (Hopewell Junction, NY); Shaw, Thomas M. (Peekskill, NY); Stone, David B. (Jericho, VT), filed on July 20, 2012, was published online on August 5, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8796133 is assigned to International Business Machines Corporation (Armonk, NY).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present disclosure relates to microelectronic packaging of semiconductor chips and, more specifically, to the process of manufacturing IC flip chip assemblies designed to reduce the structural damage to controlled collapse chip connection, also known as 'C4', connections.

"Advances in microelectronics technology tend to develop chips that occupy less physical space while performing more electronic functions. Conventionally, each chip is packaged for use in housings that protect the chip from its environment and provide input/output communication between the chip and external circuitry through sockets or solder connections to a circuit board or the like. Miniaturization results in generating more heat in less physical space, with less structure for transferring heat from the package.

"The heat of concern is derived from wiring resistance and active components switching. The temperature of the chip and substrate rises each time the device is turned on and falls each time the device is turned off. As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion (CTE), the chip and structure tend to expand and contract by different amounts, a phenomenon known as CTE mismatch. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and the printed wiring board (PWB), and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause fatigue of the electrical interconnections. This is especially true for the solder ball of the controlled collapse chip connection (C4).

"Conventional techniques for protecting structures on semiconductor chips include using low dielectric potential (k) interlevel dielectric (ILD) materials (e.g., spin-on-glass (SOG), Hydrogensilsesquioxane (HSQ), Methylisilane (MSQ), Benzocyclobutene (BCB), etc.) for input/output (I/O) and mechanical support structures that are applied to a previously fabricated semiconductor chip. Such I/O and support structures are formed after the logical function sections of the semiconductor chip have been completed. Therefore, such structures/processing are sometimes referred to as 'back end of line' (BEOL) structures/processing because they are formed at the back end of the production line.

"However, many low k materials are soft as compared to silicon dioxide and, when bonding forces are applied; the low k materials can be easily damaged. There are two main approaches to chip joining: C4 solder balls and wire bonding. In C4 joining, the forces applied during the formation of the solder ball connections, can damage the low k dielectric materials. In wire bonding, the damage from ultrasonic energy, capillary pressure, and temperature can weaken or collapse the low k insulator. Furthermore, the mechanical stresses associated with structures below the solder ball connections are such that a significant build up of stresses may result in material failure, fatigue, and eventual device breakdown. Cracking and other connection failures typically occur during chip-join, cool-down, or during subsequent handling of the flip chip package, before an underfill is introduced between the chip and package to distribute stresses across the chip/package interface more uniformly. The phenomena where cracking under the C4s occurs so as to cause the C4 sites to be highlighted in ultrasonic inspection images as white spots is sometimes referred to as 'white bumps'.

"The stress and strain of a given material are directly proportional to one another and the proportionality defines the modulus of elasticity of the material. Young's modulus (E) describes tensile elasticity, or the tendency of an object to deform along an axis when opposing forces are applied along that axis; it is defined as the ratio of tensile stress to tensile strain, and is often referred to simply as the elastic modulus.

"Empirical data and finite element modeling shows that the dielectric under C4s is more likely to crack during chip joining (white bump formation) when the effective modulus of the dielectric layers under the C4 is lower. The effective modulus of the BEOL stack depends on the modulus of the dielectric layers in the stack and the amount and arrangement of the metallization in the stack. As the modulus of the metal features is typically much higher than that of the dielectric, the effective modulus of the stack can be increased by increasing the metal density. Several configurations of the metal have been previously identified as being particularly favorable for increasing the effective modulus of the stack. These include using stacked via structures as pillar like supports and using high densities of via structures connecting metal lines and pads. Several schemes have been devised to fill blank spaces in a chip design so as to improve the stiffness of the BEOL stack. The focus of these schemes has typically been on providing a uniform overall metal density so as to enable uniform polishing of the metal structures during the CMP processing used to form Damascene interconnect structures. Approaches used include using fine square and rectangular fill shapes, filling using multiple passes with different patterns, and connecting fill shapes with via structures.

"The industry has long sought to incorporate protective structures over the semiconductor chip, or selective portions thereof, to minimize the impact of these forces on the chip structures. While techniques have been developed to avoid failure in the fill material (low k material) during manufacture, active chip devices should be shielded from mechanical stresses, especially below the solder ball connections, where significant forces are applied resulting in increased mechanical stresses in those areas."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "According to one embodiment herein, a method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4) is disclosed. The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

"According to another embodiment herein, a method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s) is disclosed. The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers being of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprising selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads, and selectively forming at least a portion of the substrate to optimize performance.

"According to another embodiment herein, a method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s) is disclosed. The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers being of low k dielectric material. The substrate has a peripheral edge and a center. The fabricating comprising selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate around the peripheral edge of the substrate and at least partly from the edge toward the center of the substrate.

"According to another embodiment herein, a semiconductor product is disclosed. The semiconductor product comprises an integrated circuit chip substrate and an interconnection layer formed between the integrated circuit chip substrate and a package. The interconnection layer comprises a plurality of controlled collapse chip connections (C4s) and an underfill material. The integrated circuit chip substrate comprises a plurality of attachment pads on a top surface thereof, and a plurality of metallization layers. One or more of the layers is of low k dielectric material. A portion of the substrate located beneath at least some of the attachment pads comprises metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material."

URL and more information on this patent, see: Bonilla, Griselda; Daubenspeck, Timothy H.; Lamorey, Mark C. H.; Landis, Howard S.; Liu, Xiao Hu; Questad, David L.; Shaw, Thomas M.; Stone, David B.. Optimization Metallization for Prevention of Dielectric Cracking under Controlled Collapse Chip Connections. U.S. Patent Number 8796133, filed July 20, 2012, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8796133.PN.&OS=PN/8796133RS=PN/8796133

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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