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Patent Issued for Multi Level Programmable Memory Structure with Multiple Charge Storage Structures and Fabricating Method

August 20, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Cheng, Cheng-Hsien (Hsinchu, TW); Tsai, Wen-Jer (Hsinchu, TW); Yan, Shih-Guei (Hsinchu, TW); Cheng, Chih-Chieh (Hsinchu, TW); Huang, Jyun-Siang (Hsinchu, TW), filed on June 22, 2011, was published online on August 5, 2014.

The patent's assignee for patent number 8796754 is MACRONIX International Co., Ltd. (Hsinchu, TW).

News editors obtained the following quote from the background information supplied by the inventors: "The invention related to a memory structure and a fabricating method thereof. More particularly, the invention relates to a memory structure having a plurality of charge storage units which is physically separated and a fabricating method thereof

"A memory is a semiconductor device designed to store information or data. As micro-processors become more functional, the programs and operations performed by software increase as well. Thus, the demand for high capacity memory becomes higher. In various memory products, non-volatile memory such as electrically erasable programmable read only memory (EEPROM) allows multiple data programming, reading, and erasing operations. Here, the data stored therein are saved even after the memory has been disconnected. According to the advantages mentioned above, EEPROM has become a memory widely adopted in personal computers and electronic apparatuses.

"In a typical EEPROM, a floating gate and a control gate are fabricated using doped polysilicon. When the memory is being programmed, electrons injected into the floating gate then distribute evenly in the entire polysilicon floating gate. However, when defects are present in a tunnel oxide layer disposed under the polysilicon floating gate, current leakage of devices then occurs easily, thereby affecting the reliability of devices.

"As a result, in order to prevent current leakage in EEPROM, a conventional method is to replace the polysilicon floating gate with a gate structure having a non-conductive charge storage layer. Another advantage of replacing the polysilicon floating gate with the charge storage layer is that when the device is being programmed, electrons are only stored locally in the charge storage layer above a source or a drain. Therefore, a source region and a control gate at one end of a stacked gate are applied with a voltage respectively during the programming so as to generate electrons with Gaussian distribution in the charge storage layer close to the source region. Moreover, a drain region at one end of the stacked gate and the control gate are also applied with a voltage respectively to generate electrons with Gaussian distribution in the charge storage layer close to the drain region. Consequently, by changing the voltage applied in the control gate and the source/drain regions at the two sides thereof, two groups of electrons with Gaussian distribution, one group of electrons with Gaussian distribution, or no electrons can be present in a single charge storage layer. Accordingly, the flash memory replacing the floating gate with the charge storage layer can be written into a single memory cell in four states and is a flash memory with a 2 bits/cell storage.

"Nevertheless, along with the increasing integrity of the semiconductor device, the dimension of the non-volatile memory is miniaturized constantly. As the miniaturization of the gate length leads to the approximation of two charge storage units located on the left and right in the same memory cell, a severe second bit effect then occurs and easily results in erroneous reading. In addition, since the source region and the drain region are miniaturized, the source region and the drain region fail to block the secondary hot electrons generated when the selected memory cell is programmed. The second hot electrode is thus injected into the adjacent memory cell to generate program disturbance and thereby lowering the reliability of memory device."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Accordingly, an embodiment of the invention provides a memory structure capable of solving the reading error caused by the second bit effect.

"Another embodiment of the invention provides a method of fabricating a memory structure capable of reducing the programming disturbance caused by secondary hot electrode.

"An embodiment of the invention provides a memory structure including a memory, and the memory cell includes the following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure, and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

"According to an embodiment of the invention, in the memory structure aforementioned, the first charge storage structure and the second charge storage structure are both two charge storage units which are physically separated, for example.

"According to an embodiment of the invention, in the memory structure aforementioned, the two charge storage units in the first charge storage structure are isolated from each other through the first dielectric structure and the two charge storage units in the second charge storage structure are isolated from each other through the second dielectric structure, for example.

"According to an embodiment of the invention, in the memory structure aforementioned, the first charge storage structure is a singular charge storage unit, for example, and the second charge storage structure includes, for instance, two charge storage units which are physically separated.

"According to an embodiment of the invention, in the memory structure aforementioned, the two charge storage units in the second charge storage structure are isolated from each other through the second dielectric structure and the first dielectric structure includes a second dielectric layer and a third dielectric layer, for example. The second dielectric layer is disposed between the first gate and the first charge storage structure and the third dielectric layer is disposed between the first charge storage structure and the channel layer.

"According to an embodiment of the invention, in the memory structure aforementioned, the first charge storage structure includes two charge storage units which are physically separated, for instance, and the second charge storage structure is a singular charge storage unit, for instance.

"According to an embodiment of the invention, in the memory structure aforementioned, the two charge storage units in the first charge storage structure are isolated from each other through the first dielectric structure and the second dielectric structure includes a fourth dielectric layer and a fifth dielectric layer, for example. The fourth dielectric layer is disposed between the channel layer and the second charge storage structure and the fifth dielectric layer is disposed between the second charge storage structure and the second gate.

"According to an embodiment of the invention, in the memory structure aforementioned, when the memory structure includes a plurality of memory cells, the memory cells are stacked.

"According to an embodiment of the invention, the memory structure aforementioned further includes a channel pick-up connected to the channel layer.

"According to an embodiment of the invention, in the memory structure aforementioned, the first gate is, for example, a first word line and the second gate is, for example, a portion of a second word line, and the second word line does not need to align the first word line.

"Another embodiment of the invention provides a method of fabricating a memory structure and the method includes the following. A first gate is formed on a substrate. A stacked structure is formed on the first gate. The stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure, and a second charge storage structure disposed in the second dielectric structure. Herein, the first charge storage structure includes two first charge storage units which are physically separated, and the second charge storage structure includes two second charge storage units which are physically separated. A first dielectric layer is formed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are formed on the first dielectric layer at two sides of the channel layer.

"According to an embodiment of the invention, in the method of fabricating the memory structure, a method of forming the first gate includes an ion implantation method or a chemical vapor deposition method, for example.

"According to another embodiment of the invention, in the method of fabricating the memory structure, a method of forming the stacked structure may include the following. A second dielectric material layer, a semiconductor material layer, a third dielectric layer, and a gate material layer are sequentially formed on the first gate. The second dielectric material layer, the semiconductor material layer, the third dielectric material layer, and the gate material layer are patterned to form a second dielectric layer, the channel layer, a third dielectric layer and the second gate sequentially on the first gate. Two sides of the second dielectric layer and two sides of the third dielectric layer are removed to form two first openings between the channel layer and the first gate and form two second openings between the second gate and the channel layer. A fourth dielectric layer is formed on a plurality of surfaces of the first openings and the second openings. The first charge storage units filling the first openings and the second charge storage units filling the second openings are formed on the fourth dielectric layer.

"According to another embodiment of the invention, in the method of fabricating the memory structure, a method of forming the fourth dielectric layer may include forming a fourth dielectric material layer on a plurality of surfaces of the first gate, the second dielectric layer, the channel layer, the third dielectric layer, and the second gate.

"According to another embodiment of the invention, in the method of fabricating the memory structure, a method of forming the first charge storage units and the second charge storage units may include the following. After the fourth dielectric material layer is formed, a charge storage material layer filling the first openings and the second openings is formed on the fourth dielectric material layer. The charge storage material layer located outside of the first openings and the second openings is removed.

"According to another embodiment of the invention, in the method of fabricating the memory structure, a method of removing a portion of the charge storage material layer is, for example, a dry etching method, a wet etching method, or a combination thereof.

"According to another embodiment of the invention, in the method of fabricating the memory structure, a method of forming the first source or drain and the second source or drain may include the following. A conductor layer covering the stacked structure is formed on the first dielectric layer. A portion of the conductor layer is removed to form the first source or drain and the second source or drain located at the two sides of the channel layer. Herein, the thicknesses of the first source or drain, the second source or drain, and the channel layer are substantially the same, for example.

"According to another embodiment of the invention, in the method of fabricating the memory structure, a fifth dielectric layer located at the two sides of the second gate is formed on the first source or drain and the second source or drain.

"According to another embodiment of the invention, in the method of fabricating the memory structure, a method of forming the fifth dielectric layer may include the following. A fifth dielectric material layer is formed on the first source or drain and the second source or drain and the fifth dielectric material layer covers the stacked structure. A portion of the fifth dielectric material layer is removed until the second gate is exposed.

"According to another embodiment of the invention, the method of fabricating the memory structure aforementioned further includes forming a connecting lead on the second gate and the second gate forms a word line with the connecting lead.

"In light of the foregoing, in the memory structure disclosed in one embodiment of the invention, as at least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated, the reading error caused by the second bit effect can be prevented and the programming disturbance led by the secondary hot electrode can be reduced.

"Moreover, another embodiment of the invention disclosed a fabricating method of a memory structure which can be integrated with the conventional fabrication. As a consequence, the fabrication complexity is decreased effectively.

"In order to make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below."

For additional information on this patent, see: Cheng, Cheng-Hsien; Tsai, Wen-Jer; Yan, Shih-Guei; Cheng, Chih-Chieh; Huang, Jyun-Siang. Multi Level Programmable Memory Structure with Multiple Charge Storage Structures and Fabricating Method. U.S. Patent Number 8796754, filed June 22, 2011, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8796754.PN.&OS=PN/8796754RS=PN/8796754

Keywords for this news article include: Electronics, Semiconductor, MACRONIX International Co. Ltd..

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Source: Electronics Newsweekly


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