News Column

Patent Issued for Methods and Apparatuses for Processing Cached Image Data

August 21, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Chin, Yunsen (Fremont, CA); Wang, Haohong (San Jose, CA), filed on April 19, 2013, was published online on August 5, 2014.

The patent's assignee for patent number 8797343 is Marvell International Ltd. (Hamilton, BM).

News editors obtained the following quote from the background information supplied by the inventors: "Some conventional graphics processing schemes include dividing a graphics surface into a plurality of pixels, each pixel representing the smallest dimension or block of information of the graphics surface. Typically, a pixel comprises discrete portions or components representative of the color, transparency, hue, saturation, brightness, chrominance, luminance, intensity, and/or other visual parameters. For example, an RGB pixel is based on an additive color model and comprises portions corresponding to red, green, and blue channel(s). In other examples, an RGBA pixel is based on an additive color model and comprises portions corresponding respectively to red, green, blue, and alpha channels, where the alpha channel represents the transparency of the pixel. In yet other examples, a CMYK pixel is based on a subtractive color model and comprises portions corresponding respectively to cyan, magenta, yellow, and black channels. In other examples, a HSV pixel is based on a transformed RBG color model, where each pixel comprises portions corresponding respectively to hue, saturation, and value channels.

"In some conventional digital graphics processes, each channel of a pixel may be represented by or discretized into a digital value. In some examples, a 32-bit RGBA pixel may comprise 8 binary bits for each of a red color component (or channel), a green color component (or channel), a blue color component (or channel), and an alpha channel. In such examples, each channel can be partitioned into one of 256 (or 2^8) values. In other examples, a 32-bit RGBA pixel may comprise 10 binary bits for each of a red color component, a green color component, and a blue color component, and two bits for an alpha channel. In such examples, each of the red, green, and blue channels can be partitioned into one of 1024 values, and the alpha channel can be partitioned into one of four transparency percentage values.

"Some conventional graphics processing devices include a pixel memory for storing individual pixels of the graphics surface. When it is desired to perform a mathematical operation on the contents of a pixel, the pixel is generally first read from pixel memory into a memory of the graphics processor, which performs the mathematical operation. Generally, the transformed and/or modified pixel is then written back to pixel memory, or in the case where the pixel is to be displayed on a monitor or other display device, written to a memory associated with the monitor. When a mathematical operation is to be simultaneously performed on more than one pixel of the graphics surface, each pixel is generally read first, before the operation can occur. Thus, some conventional graphics processing devices further divide the graphics surface into a plurality of tiles, each tile representing one or more adjacent pixels. For example, a tile may represent a block of four pixels--two pixels wide by two pixels high. In other examples, a tile may represent a block of sixty four pixels--eight pixels wide by eight pixels high.

"Referring to the illustration of FIG. 1, a conventional graphics surface 10 can be divided into M*N tiles, each tile T.sub.i,j of which may be representative of one or more pixels. Typically, each tile represents the same number of pixels. For example, each tile may represent 64 pixels. However, it is possible that different tiles in the surface 10 may represent different numbers of pixels.

"As shown in the illustration of FIG. 2, a conventional tile 20 can represent J*K pixels, each pixel P.sub.m,n of which may have discrete portions or components representative of visual parameters (e.g., definitional color model channels). Typically, the same definitional color model (e.g., set of possible visual parameter values) applies to each pixel of a graphics surface. However, it is possible that different definitional color models may apply to different pixels.

"Referring to the illustration of FIG. 3, in some implementations, a conventional pixel 30 (e.g., P.sub.m,n) can include a red color channel 31, a green color channel 33, a blue color channel 35, and an alpha channel 37. In some digital examples, each of channels 31, 33, 35, and 37 may have the same number of bits, while in other examples, the various channels may have the same or different numbers of bits.

"Some conventional graphics processing schemes are not optimized to perform efficient operations on a graphics surface. For example, a conventional graphics surface may have a resolution of 1920 pixels wide by 1080 pixels high and use 32-bit RGBA color model. The graphics surface may be divided into 32,000 tiles, wherein each tile is 8 pixels wide by 8 pixels high. Referring then together to the illustrations of FIGS. 1-3, the graphics surface 10 may be divided into 240 tiles wide by 135 tiles high (i.e., M=240, N=135), each tile 20 being 8 pixels wide by 8 pixels high (i.e., J=8, K=8), and each pixel 30 having 8 bits for each of a red channel 31, green channel 33, blue channel 35, and alpha channel 37. It is to be appreciated that the memory access for a single pixel is 4 Bytes (i.e., 32 bits), that the memory access for one tile (or 64 pixels) is 256 Bytes, and that the memory access for the entire surface (or 32,000 tiles) is 8 MB.

"Depending on the graphics surface, it may be common for one or more tiles to have pixels having the same value. For example, each pixel of a tile may be colored red. In some conventional graphics processing schemes, regardless of whether the individual pixels have the same value, the entire tile must be read from, or written to, pixel memory. Thus, for example, although there may be only 4 Bytes of unique information (corresponding to the value of the red pixel), the size of the memory access is still 256 Bytes. Extending the example further, if a graphics surface having a solid color is to be stored in pixel memory, some conventional graphics processing schemes would require a memory access of the full 8 MB. By inefficiently reading and/or writing to pixel memory, system throughput is non-optimal and energy consumption may be unnecessarily high."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "More specifically, embodiments of the present invention pertain to methods and apparatuses for processing image data. More particularly, embodiments of the present invention concern methods, software, and apparatuses for caching pixel values of at least one tile of a graphics surface when the pixels of the tile have a common pixel value.

"In some embodiments, a method for processing a graphics surface includes setting a pattern caching bit corresponding to the surface; setting P tile pattern bits; and when the pattern caching bit is in an active state, storing V pixel values in a cache memory. For example, the pattern caching bit may be associated with each graphics surface stored in pixel memory (or other memory, such as a hard disk drive or flash memory). Generally, the graphics surface has a plurality of tiles, and each tile has a plurality of pixels. In addition, each of the P tile pattern bits and each of the V pixel values generally correspond to at least one of the T tiles. The pixel values may comprise one or more channel or component values, such as blue, green, red, or alpha channel values, or alternatively, one or more cyan, magenta, yellow, or black channel values. Additionally or alternatively, the pixel values may comprise one or more transparency, hue, saturation, brightness, intensity, luminosity, or chrominance channel values. The pattern caching bit may indicate when pattern caching (e.g., storing a common pixel value for pixels in one or more tiles in cache memory) is active for a particular graphics surface. For example, and without limitation, the pattern caching bit may have a first state when pattern caching is active and a second state when pattern caching is inactive. In one advantageous embodiment, the pixel values are the same for all channels in each pixel in the tile. In some embodiments, when at least one of the P tile pattern bits corresponds to a plurality of the T tiles of the graphics surface, the P tile pattern bits may be decoded into T tile pattern bits, wherein each of the T tile pattern bits corresponds to one of the T tiles.

"In further embodiments, the method can further include initializing the pattern caching bit and each of the P tile pattern bits to an inactive state. Furthermore, each of the V pixel values may be initialized to an initial value. The pattern caching bit may be set to the active state when at least one channel or component of all pixels of at least one of the tiles (and in a particularly advantageous case, all of the channels or components of each pixel) have a common or identical pixel value. In some examples, and without limitation, the pattern caching bit may comprise a logic value (such as a digital '1' or '0' bit) stored in a memory such as a register. In other examples, the pattern caching bit may comprise a signal in a graphics processing unit or other graphics device.

"In further embodiments, the method further includes setting at least one of the P tile pattern bits corresponding to the tile(s) having the common or identical pixel value to an active state; and setting one or more of the V pixel values corresponding to the tile(s) having the common or identical pixel value to the common or identical pixel value. In some further embodiments, when all of the pixels of a plurality of the tiles have a common or identical pixel value, at least one of the P tile pattern bits corresponding to the plurality of tiles may be set to an active state, and at least one of the V pixel values corresponding to the tiles having the common or identical pixel value may be set to the common or identical pixel value.

"Thus, in some embodiments of the present invention, each of the P tile pattern bits indicates when each of the pixels of one or more of the tiles has the same (i.e., a common and/or identical) value. In some examples, and without limitation, the P tile pattern bits may comprise logic values (such as a digital '1' or '0' bit) stored in a cache memory such as a register or random access memory (RAM). In other examples, the P tile pattern bits may comprise one or more signals in a graphics processing unit or other graphics device. However, other techniques for implementing the pattern caching bit and/or the tile pattern bits are contemplated in accordance with embodiments of the present invention.

"In some embodiments, a tile may be read by reading from the cache memory at least one of the V pixel values corresponding to the tile when at least one of the P tile pattern bits corresponding to the tile is set to an active state. In some embodiments, when all of the pixels (or one or more channels or components of the pixels) of a destination tile have a common and/or identical pixel value, the destination tile may be written to the surface by determining whether any of the P tile pattern bits corresponding to the destination tile have an active state, and if at least one tile pattern bit is active, reading the V pixel value(s) corresponding to the destination tile from the cache memory. In some embodiments, an entirety of the surface may be filled with a specific common or identical pixel value by setting the pattern caching bit to an active state; setting each of the P tile pattern bits to an active state; and setting each of the V pixel values to the common or identical pixel value.

"In some embodiments (e.g., relating to identifying or generating the data to be stored in the cache memory), a source tile pattern bit corresponding to a source tile may be set and a source cache pixel may be stored in the cache memory. The source tile generally includes a plurality of source pixels, and when all of the source pixels of the source tile have a common or identical pixel value, the source pixel value may correspond to the V pixel value(s) having the common or identical pixel value. In some embodiments, the source tile pattern bit may be set to at least one of the P tile pattern bits corresponding to one of the tiles of the graphics surface, and the V pixel value(s) corresponding to the tile(s) of the graphics surface may be copied to the cache memory. If all of the source pixels of the source tile has a common or identical pixel value, the source tile pattern bit may be set to an active state, and the source pixel value may be set to the common or identical pixel (e.g., color) value.

"In some embodiments, a graphics operation may be performed on the source tile and a destination tile of the graphics surface. For example, when the source tile pattern bit is set to an active state and the source pixels have a value comprising a portion indicating that a corresponding pixel of said destination tile is not changed (e.g., an alpha value equal to zero), the graphics operation may include the step of not modifying the destination tile. In some embodiments, when the source tile pattern bit is in an active state, a destination tile of the graphics surface may be filled with the source tile by reading the source pixel value from the cache memory, and writing the source pixel value to each pixel of the destination tile. In some embodiments (e.g., a so-called 'non-tile aligned' copy operation), when the source tile pattern bit is set to an active state, a source copy operation that partially fills a destination tile of the graphics surface with a portion of the source tile may include setting at least one of the P tile pattern bits of the graphics surface corresponding to the destination tile to an inactive state, and writing to non-tile-aligned pixels of the destination tile the source pixel value.

"The software, architectures, apparatuses, and/or systems generally comprise those that embody one or more of the inventive concepts disclosed herein. For example, one aspect of the invention may relate to a computer-readable medium having encoded thereon a computer executable set of instructions adapted to process a graphics surface comprising a tile array, wherein each tile in the array comprises a plurality of pixels that may be stored in pixel memory (or other memory, such as a hard disk drive or flash memory). In general, the instructions comprise determining whether each of the plurality of pixels in one or more tiles in the array has a common or identical value for one or more predetermined parameters, channels or components, setting a caching bit corresponding to the surface to a first value when each pixel of at least one of the one or more tiles has the same value, setting one or more tile pattern bits to a first state when the caching bit has the first value, the one or more tile pattern bits corresponding to at least one of the one or more tiles in which each pixel has the same value, and storing in cache memory the value of the pixels for each of the one or more tiles in which each pixel has the same value in accordance with the caching bit and the one or more tile pattern bits.

"In a further embodiment, when the caching bit has the first value, the instructions may further be adapted to provide the one or more tiles having corresponding pattern bits set to the first value to an image processing function by retrieving the value of the pixels from the cache memory. When the caching bit has the first value, the instructions may further comprise retrieving the value of the pixels from the cache memory for each tile having corresponding pattern bits set to the first state, and providing the value of the pixels for each such tile to an image processing function. In some embodiments, the instructions may further comprise setting the caching bit to a second state when each of the tiles contains at least two pixels having different values for at least one of the predetermined parameters, channels or components. In one example, the instructions set the caching bit to a second state when each of the tiles contains at least two pixels having different values for each of the predetermined parameters, channels or components. Thus, in some embodiments, the instructions may further comprise retrieving the value of each of the pixels from a pixel memory and providing each of the pixel values to an image processing function for each of the tiles having corresponding tile pattern bits set to the second state, storing the plurality of pixels of at least one of the one or more tiles of the graphics surface in a pixel memory, and/or performing the image processing function using the plurality of pixels.

"A still further aspect of the invention relates to an image processing apparatus, comprising a pixel memory, a cache memory, and a controller configured to operate on a graphics surface comprising T tiles, each tile comprising a plurality of pixels stored in the pixel memory. The controller generally includes logic configured to reserve in the cache memory a caching bit, P tile pattern bits, and an array of pixel values, wherein each of the P tile pattern bits corresponds to at least one of the T tiles of the graphics surface. The controller logic may be further configured to determine whether each of the pixels of one or more of the T tiles has a common or identical value, and when each of the pixels of at least one of the T tiles has the same value, set each of the P tile pattern bits corresponding to such tile(s) to an active state and storing the common or identical pixel value in the cache memory. In one embodiment, the controller further includes logic configured to initialize the caching bit and each of the tile pattern bits to an inactive state.

"The present invention provides for improved memory access bandwidth during graphics operations by reducing the tile memory access to a single pixel access if the tile is determined to have a predetermined pattern. In addition, the invention provides for totally skipping a tile memory access if the pixel values of the destination tile do not change. These and other advantages of the present invention will become readily apparent from the detailed description of preferred embodiments below."

For additional information on this patent, see: Chin, Yunsen; Wang, Haohong. Methods and Apparatuses for Processing Cached Image Data. U.S. Patent Number 8797343, filed April 19, 2013, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8797343.PN.&OS=PN/8797343RS=PN/8797343

Keywords for this news article include: Software, Marvell International Ltd..

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