The assignee for this patent, patent number 8796853, is
Reporters obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to a semiconductor structure and a method of forming the same. More particularly, the present disclosure relates to an interconnect structure including a metallic cap located atop a conductive metal feature of the interconnect structure.
"Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene interconnect structures. The interconnect structure typically includes copper, Cu, or a Cu alloy since Cu-based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al,-based interconnects.
"Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as 'crosstalk') is achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
"In semiconductor interconnect structures, electromigration (EM) has been identified as one metal failure mechanism. Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size decreases, the practical significance of EM increases.
"EM is one of the worst reliability concerns for very large scale integrated (VLSI) circuits and manufacturing since the 1960's. The problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip. Voids are created inside the metal conductors of an interconnect structure due to metal ion movement caused by the high density of current flow.
"Although the fast diffusion path in metal interconnects varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that metal atoms, such as Cu atoms, transported along the metal/post planarized dielectric cap interface play an important role on the EM lifetime projection. The EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction to the bottom of the interconnect, which eventually results in a circuit dead opening.
"It has been demonstrated that by replacing the Cu/dielectric interface with a Cu/metal interface can enhance electromigration resistance by greater than 100.times.. Prior art metal caps are typically comprised of a Co-containing alloy such as, for example, CoWP, which is selectively deposited atop of the Cu conductor region of the interconnect structure utilizing plating, chemical vapor deposition or atomic layer deposition. One problem with utilizing such selectively deposited metal caps is that some of the metal cap extends onto the adjoining surface of the interconnect dielectric material and, as such, electrical shorts between adjacent interconnects may arise.
"It is also known to provide a metal cap directly on the surface of an interconnect conductive material, such as, for example, Cu, by recessing the interconnect conductive material below a surface of the interconnect dielectric material. Although this prior art process provides a metal cap that is located only on a surface of the recessed conductive material, such a process is problematic since there is high process cost associated therewith.
"It is further known to provide a metal cap utilizing a CuMn alloy which is first deposited within an opening of an interconnect dielectric material and then an anneal is performed to migrate the Mn upwards to form a metallic cap that is composed of Mn atop a Cu structure that has a reduced Mn content. This prior art approach can negatively impact the electrical conductivity of the interconnect structure."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.
"The interconnect structure of the present disclosure provides reduced electromigration (EM) and, as such, EM void growth is also reduced. The aforementioned properties are achieved in the present disclosure without increasing the resistance of the interconnect structure and without utilizing complex processes such as is required in prior art processes. In some embodiments, the interconnect structure of the present disclosure does not exhibit any undesirable line-to-line leakages or capacitance increases.
"In one aspect of the present disclosure, an interconnect structure is provided. The interconnect structure includes an interconnect dielectric material having an opening located therein. A diffusion barrier is located on wall surfaces of the interconnect dielectric material within the opening. A conductive metal feature is located on the diffusion barrier and partially fills the opening. A metallic cap is located on a portion of the conductive metal feature within the opening. The conductive metal feature has laterally extending portions that are located on each vertical edge of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.
"In another aspect of the present disclosure, a method of providing an interconnect structure is provided. The method includes providing a structure including an interconnect dielectric material having an opening located therein. A diffusion barrier is then formed on an uppermost surface of the interconnect dielectric material and on wall portions of the interconnect dielectric material within the opening. Next, a contiguous conductive metal liner is formed on the diffusion barrier that is located on the uppermost surface of the interconnect dielectric material and on the wall portions of the interconnect dielectric material within the opening. A reflow anneal is then performed which causes a portion of the contiguous conductive metal liner that is located outside the opening to flow into the opening and to partially fill the opening with a conductive metal. A cavity remains within the opening after the reflow anneal. A metallic layer is formed within the cavity and atop remaining portions of the contiguous conductive metal liner that are located atop the diffusion barrier that is located outside the opening and on the uppermost surface of the interconnect dielectric material. A portion of the metallic layer, remaining portions of the contiguous conductive metal liner, and a portion of the diffusion barrier that are located outside of the opening are then removed to provide a metallic cap located on a portion of a conductive metal feature within the opening. The conductive metal feature that is provided has laterally extending portions located on each vertical edge of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap."
For more information, see this patent: Yang, Chih-Chao; Hu, Chao-Kun. Metallic Capped Interconnect Structure with High Electromigration Resistance and Low Resistivity. U.S. Patent Number 8796853, filed
Keywords for this news article include: Electronics, Semiconductor,
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