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Patent Issued for Memory System Having Delay-Locked-Loop Circuit

August 20, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Choi, Jung-Hwan (Hwaseong-si, KR), filed on February 20, 2014, was published online on August 5, 2014.

The assignee for this patent, patent number 8797812, is Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "Embodiments relate to a semiconductor device, and more particularly, to a semiconductor device and a memory system having a delay-locked-loop circuit.

"A delay-locked-loop (DLL) circuit is a circuit that generates an internal clock signal synchronized with an external clock signal through a synchronizing process based on a delay amount of a signal.

"Semiconductor memory devices such as dynamic random access memories (DRAMs) are used for storing data in computers and electronic products. Data is written to a DRAM device during a write operation mode, and is read from the DRAM during a read operation mode. The output circuit of the DRAM device needs a clock signal such as a data strobe (DS) signal when data is read from the DRAM device. An internal clock signal synchronized with an external clock signal is needed to output the data exactly. Recently, in semiconductor memory devices such as DRAM devices, a clock signal used in the semiconductor memory device is synchronized with the output clock signal by a DLL circuit."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "It is a feature of an embodiment to provide a delay-locked-loop (DLL) circuit that stores locking information of an external clock signal having a low frequency and locking information of an external clock signal having a high frequency beforehand, and generates an internal clock signal synchronized with the external clock signal using the locking information during a subsequent operation.

"It is a separate feature of an embodiment to provide a DLL circuit in which a time required to synchronize the internal clock signal with the external clock signal may be relatively short when the external clock signal changes from low frequency to high frequency or from high frequency to low frequency.

"It is a separate feature of an embodiment to provide a semiconductor device and/or a system including the DLL circuit that may operate at a relatively higher speed relative to comparable conventional devices.

"It is a separate feature of an embodiment to provide a semiconductor device including a DLL circuit that stores locking information of an external clock signal having a low frequency and locking information of an external clock signal having a high frequency beforehand, and generates an internal clock signal synchronized with the external clock signal using the locking information in a later operation.

"It is a separate feature of an embodiment to provide a memory system including a DLL circuit that stores locking information of an external clock signal having a low frequency and locking information of an external clock signal having a high frequency beforehand, and generates an internal clock signal synchronized with the external clock signal using the locking information during a subsequent operation.

"At least one of the above and other features and advantages may be realized by providing

"In accordance with an aspect of the inventive concept, a DLL circuit includes a first DLL and a second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

"In an embodiment, the first DLL may store locking information of the first internal clock signal having a low frequency and the second DLL may store locking information of the second internal clock signal having a high frequency. In a subsequent operation, the DLL circuit may generate an internal clock signal synchronized with the external clock signal using the locking information of the first internal clock signal and the locking information of the second internal clock signal.

"In an embodiment, the first DLL and the second DLL may operate in response to a mode register set signal.

"In an embodiment, the locking information of the first internal clock signal may be a delay amount of a delay line of the first DLL, and the locking information of the second internal clock signal may be a delay amount of a delay line of the second DLL.

"In an embodiment, the DLL circuit may further include a selecting circuit that selects one of the first internal clock signal and the second internal clock signal to generate an internal clock signal.

"In an embodiment, the first DLL may include a phase detector, a delay control circuit and a delay line.

"The phase detector may compare the external clock signal and a feedback signal to generate an up signal and a down signal. The delay control circuit may store locking information for a clock signal having the low frequency, and generate delay control signals based on the up signal and the down signal. The delay line may delay the external clock signal to generate the first internal clock signal in response to the delay control signals.

"In an embodiment, the delay control circuit may operate when the external clock signal has a low frequency, and may not operate when the external clock signal has a high frequency.

"In an embodiment, the first DLL may further include a replica path that delays the first internal clock signal to generate the feedback clock signal.

"In an embodiment, the second DLL may include a phase detector, a delay control circuit and a delay line.

"The phase detector may compare the external clock signal and a feedback signal to generate an up signal and a down signal. The delay control circuit may store locking information for a clock signal having the high frequency, and generate delay control signals based on the up signal and the down signal. The delay line may delay the external clock signal to generate the second internal clock signal in response to the delay control signals.

"In an embodiment, the delay control circuit may operate when the external clock signal has a high frequency, and may not operate when the external clock signal has a low frequency.

"In accordance with another aspect of the inventive concept, a DLL circuit includes a first DLL and a second DLL. The first DLL adjusts a delay time of a first external clock signal having a low frequency received from a first input terminal to generate a first internal clock signal synchronized with the first external clock signal. The second DLL adjusts a delay time of a second external clock signal having a high frequency received from a second input terminal to generate a second internal clock signal synchronized with the second external clock signal.

"In accordance with still another aspect of the inventive concept, a semiconductor device includes a DLL circuit and an internal circuit. The DLL circuit generates an internal clock signal synchronized with an external clock signal and the internal circuit operates in response to the internal clock signal. The DLL circuit includes a first DLL and a second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

"In an embodiment, the semiconductor device may be a semiconductor memory device.

"In an embodiment, the internal circuit may be an output circuit of the semiconductor memory device.

"In accordance with yet another aspect of the inventive concept, a memory system includes a memory controller and a semiconductor memory device which transmits to or receives from the memory controller. The semiconductor memory device includes a DLL circuit for generating an internal clock signal synchronized with an external clock signal, and an internal circuit operating in response to the internal clock signal. The DLL circuit includes a first DLL and a second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency."

For more information, see this patent: Choi, Jung-Hwan. Memory System Having Delay-Locked-Loop Circuit. U.S. Patent Number 8797812, filed February 20, 2014, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8797812.PN.&OS=PN/8797812RS=PN/8797812

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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