News Column

Patent Issued for Control of Digital Voltage and Frequency Scaling Operating Points

August 21, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- Ericsson Modems SA (Le Grand-Saconnex, CH) has been issued patent number 8799698, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Singvall, Jakob (Bjarred, SE); Bauer, Harald (Nuremberg, DE).

This patent was filed on May 31, 2011 and was published online on August 5, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to the control of power expenditure in electronic circuitry, and more particularly to the control of clock frequency and voltage supply operating points in electronic circuitry.

"Dynamic voltage and frequency scaling (DVFS) is a well-known principle in electronic circuit design: Clock frequency as well as voltage supply are scaled to the minimum values necessary to satisfy application performance requirements. Power savings occur across the total hardware component (not only at the clock related circuitry as for clock gating and frequency scaling techniques) and are significant due to the quadratic effect that voltage changes have on power consumption. A DVFS operating point (OPP) is defined by a predetermined clock frequency/voltage level pair. Several, or at least two, OPPs are defined for circuitry employing DVFS, with one of the OPPs being operative at any given time.

"For a given circuit/component, selection of an OPP is made on a per application use case basis. Examples of use cases include, but are not limited to: a phone being used for making a call a phone being used for web browsing a phone being in idle mode (i.e., switched on but not being used and capable of responding to an incoming call

"Selection of an OPP for a given use case is guided by the following principles: It is desired to avoid selecting an OPP having too low a clock frequency and/or too low a supply voltage value because this may cause violation of application real-time constraints. It is desired to avoid selecting an OPP having a clock frequency and/or supply voltage value higher than that which is required to satisfy application requirements because this results in higher than necessary energy consumption. This is due to the fact that the higher the clock frequency, the higher the required supply voltage value, and this higher supply voltage value in turn results in higher energy consumption.

"The inventors of the subject matter described herein have recognized that there are a number of problems with existing DVFS technology. One is that, with a limited number of defined OPPs, the mapping of application use cases to OPP may not be optimal. For example, assume that an embodiment has two defined OPPs, with OPP1 calling for a clock frequency of 100 MHz and OPP2 calling for a clock frequency of 50 MHz. Use cases that map to OPP1 (i.e., those with requirements calling for a clock frequency greater than 50 MHz) will therefore not benefit from DVFS because there will be no power reduction.

"With the two OPPs as described, sub-optimal performance results because the worst case real time deadline within a use case will cause selection of the effective OPP to be OPP1 even if most of the time the use case can be running at a lower frequency.

"Another detriment is that OPP frequency and voltage may be set early on in a project based on estimations of application requirements. Later on, due to changed requirements, the frequency and voltage may not be optimal from a power consumption perspective. It is therefore desired to have methods and apparatuses that achieve more optimal performance under the changed requirements.

"The inventors of the subject matter described herein have further recognized that often a higher clock frequency is needed only for a very short period of time. However, switching from one OPP to another during this short period of time might result in significant overhead if OPP switching is implemented by means of a software-controlled processor.

"An example of this problem arises in the context of the Long Term Evolution (LTE) system's 'Micro Sleep'. The basic idea is to power-down the receiver path in the radio as soon it is detected that no data packet needs to be received in the current transmission time interval (TTI). This requires decoding of the control channel as fast as possible using the highest possible clock frequency. In this use case, OPP1 is required only during decoding of the control channel. The remaining time, OPP2 can be used. As control channel decoding takes only a very short amount of time, changing from one OPP to another in a software-controlled implementation would cause a lot of overhead.

"It is therefore desired to provide DVFS control mechanisms that provide for the use of optimal OPPs without the overhead found in conventional implementations."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "It should be emphasized that the terms 'comprises' and 'comprising', when used in this specification, are taken to specify the presence of stated features, integers, steps or components; but the use of these terms does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

"In accordance with one aspect of the present invention, at least some of the foregoing and other objects are achieved in methods and apparatuses for generating a clock signal to be supplied to electronic circuitry. This involves generating, based on which one of a plurality of application use cases capable of being carried out by the electronic circuitry is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points should be active. Also, based on a present speed requirement of the electronic circuitry, a second signal is generated that indicates a second selected one of the plurality of clock signal operating points. For any given one of the application use cases, the present speed requirement need not remain constant for the duration of the given one of the application use cases. Based on the first and second signals, a third signal is generated that indicates which of the plurality of clock signal operating points should be active, wherein the clock signal operating point indicated by the third signal is whichever one of the clock signal operating points indicated by the first and second signals is associated with a higher clock signal frequency. The third signal is used to control generation of a clock signal having the operating point indicated by the third signal.

"In some embodiments, the first signal further indicates a first selected one of a plurality of supply voltage levels; the second signal further indicates a second selected one of the plurality of supply voltage levels; the third signal further indicates which of the plurality of supply voltage levels should be active; and the third signal is used to control generation of a supply voltage level having the supply voltage level indicated by the third signal.

"In some alternative embodiments, the first signal further indicates a first selected one of a plurality of supply voltage levels; the second signal further indicates a second selected one of the plurality of supply voltage levels; and generation of the clock signal further comprises generating, based on the first and second signals, a fourth signal that indicates which of the plurality of supply voltage levels should be active, wherein the supply voltage level indicated by the fourth signal is the most power consuming one of the supply voltage level indicated by the first signal and the supply voltage level indicated by the second signal; and using the fourth signal to control generation of a supply voltage level having the supply voltage level indicated by the fourth signal.

"In some embodiments, the first signal has two states; the second signal has two states; and generating the third signal that indicates which of the plurality of clock signal operating points should be active comprises performing a logical OR between the first signal and the second signal.

"In some embodiments, the first signal has more than two states and the second signal has more than two states.

"In some embodiments, generating the first signal comprises using a programmed processor to select one of the plurality of clock signal operating points based on which of the plurality of application use cases is presently active; and generating the second signal comprises using a hardwired component to generate the second signal based on the present speed requirement of the electronic circuitry. In some but not necessarily all of these embodiments, the hardwired component is a timing generator.

"In some embodiments, the electronic circuitry is configured to perform functions in a mobile communication equipment; and the present speed requirement of the electronic circuitry is a function of a timing characteristic of a signal received by the mobile communication equipment.

"In some embodiments, the third signal is also used to control generation of one or more other clock signals, each having the clock signal operating point indicated by the third signal, wherein for any given one of the plurality of clock signal operating points, the clock signal and the one or more other clock signals operate at different frequencies relative to one another.

"In some embodiments, the third signal is also used to control generation of one or more other supply voltage levels, wherein for any given one of the plurality of supply voltage levels, the generated supply voltage level and the generated one or more other supply voltage levels are different from one another.

"In some embodiments, the second signal changes states while the first signal remains constant during the given one of the application use cases, whereby an average clock frequency during the given one of the application use cases is not equal to any one of a plurality of clock frequencies that respectively correspond to the clock signal operating points.

"In some embodiments, generation of the second signal based on the present speed requirement of the electronic circuitry is inhibited, and instead the second signal is generated as a pulse width modulated signal having a duty cycle that is based on the presently active application use case. In some but not necessarily all of these embodiments, the first signal is caused to remain in a deasserted state for the duration of the presently active application use case."

For the URL and additional information on this patent, see: Singvall, Jakob; Bauer, Harald. Control of Digital Voltage and Frequency Scaling Operating Points. U.S. Patent Number 8799698, filed May 31, 2011, and published online on August 5, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8799698.PN.&OS=PN/8799698RS=PN/8799698

Keywords for this news article include: Software, Ericsson Modems SA.

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Source: Computer Weekly News


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