The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "The disclosure relates to a layout decomposition method and method for manufacturing a semiconductor device applying the same.
"With a continuing development of reduce-sized electrical devices, the features such as integrated circuits (ICs) thereon are being made smaller and smaller. The fine pitches and patterns of features are required to satisfy the demands of the smaller devices. However, the required fine pitches and patterns of features raise the difficulty of the device fabrication. The feature size reduction could be limited due to the conventional processing techniques; for example, photolithography techniques have a minimum pitch below which features cannot be formed reliably. Generally, the ability to project an accurate image of increasingly smaller features onto the substrate/wafer is limited by the wavelength of the light used in photolithography, and the ability of the lens system. The yield of the photolithographic process gradually decreases, and its cost increases, as k1, a dimensionless coefficient of process-related factor, decreases below 0.35. Reducing k1 below 0.28 for a single exposure is not practical. Typically, double exposure is adopted for forming the features containing fine patterns and large patterns on a device.
"Also, the 'pitch doubling' technique has been proposed for extending the capabilities of photolithographic techniques beyond their minimum pitch, and it allows the number of features in a region of the substrate to be doubled. However, the doubled features formed by the 'pitch doubling' technique would cause the problem to the areas requiring forming the odd-numbered features."
In addition to obtaining background information on this patent application, NewsRx editors also obtained the inventor's summary information for this patent application: "The disclosure is directed to a layout decomposition method and a method for manufacturing a semiconductor device applying the same. The layout decomposition method including step of identifying areas of odd-numbered features. The method for manufacturing semiconductor device applying the layout decomposition method of the embodiment simply transfers the patterns containing odd-numbered features of the semiconductor device.
"According to the disclosure, a layout decomposition method executed by a logic processor of a computing system is provided. First, a design layout is received by the logic processor. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas.
"According to the disclosure, a method for manufacturing a semiconductor device, involving a layout decomposition executed by a logic processor of a computing system, is provided. In the beginning, a design layout is received and analyzed by the logic processor. Then dense areas (areas with densely distributed features) on a substrate, and also areas with odd-numbered features on the substrate are identified according to analyzing results of the design layout by the logic processor. At least two groups of odd-numbered features are formed respectively in at least two of the identified areas with odd-numbered features in one of the identified dense areas. This is achieved by the following steps. First, a temporary layer on the substrate is exposed through a first mask having a first pattern for fabricating patterns of spacers at least in one of the identified dense areas of the substrate, and the temporary layer is developed to form placeholders on the substrate. Then, even-numbered features are formed in the one of the identified dense areas of the substrate by at least a step of depositing a spacer material over the placeholders on the substrate, and a step of patterning the spacer material to form even-numbered spacers in the one of the dense areas of the substrate. After that, odd-numbered features of the even-numbered features are cut and/or blocked and part of the odd-numbered features is removed through a second mask having a second pattern, so as to form the at least two groups of odd-number features.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 shows a flowchart of a general process for a layout decomposition method according to the embodiment of the disclosure.
"FIG. 2A-FIG. 2D schematically illustrate an example for partially manufacturing a device with even-numbered features on a dense area according to the embodiment of the disclosure.
"FIG. 3A-FIG. 3D schematically illustrate an approach for partially manufacturing a device with odd-numbered features on a dense area according to the embodiment of the disclosure.
"FIG. 4A-FIG. 4D schematically illustrate another approach for partially manufacturing a device with odd-numbered features on a dense area according to the embodiment of the disclosure.
"FIG. 5 illustrates a second mask for transferring pattern of spacers to the substrate.
"FIG. 6A illustrates another second mask adopted for subsequently transferring pattern of spacers of FIG. 4D.
"FIG. 6B illustrates a patterned substrate after spacer pattern transformation.
"FIG. 7A-FIG. 11 schematically illustrate still another approach for partially manufacturing a device with odd-numbered features on a dense area according to the embodiment of the disclosure."
For more information, see this patent application: Tung, Yu-Cheng. Layout Decomposition Method and Method for Manufacturing Semiconductor Device Applying the Same. Filed
Keywords for this news article include: Semiconductor, Photolithography,
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