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Researchers Submit Patent Application, "Semiconductor Apparatus, Test Method Using the Same and Muti Chips System", for Approval

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor KIM, Dae Suk (Icheon-si, KR), filed on March 18, 2013, was made available online on July 3, 2014.

The patent's assignee is Sk Hynix Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a semiconductor apparatus and a test method using the same.

"A general semiconductor apparatus, for example, a semiconductor memory apparatus is configured to store data and output the stored data. In order to increase a data storage capacity of a semiconductor apparatus, a semiconductor apparatus in which memory dies for storing data are stacked has been used.

"Referring to FIG. 1, a conventional semiconductor apparatus includes first to third memory dies 10 to 30 which are sequentially stacked.

"The stacked first to third memory dies 10 to 30 are coupled to each other through through-silicon vias (TSVs). For example, the conventional semiconductor apparatus may include a plurality of data input/output TSVs DQ_TSV1, DQ_TSV2, and DQ_TSV3 as shown in FIG. 1.

"The semiconductor apparatus configured in such a manner is commercialized and launched on the market, depending on a result obtained by testing whether or not the respective memory dies 10 to 30 normally store and output data.

"A method for testing whether or not the respective memory dies 10 to 30 normally store and output data is performed as follows. First, the same data are stored in the respective memory dies 10 to 30, one of the first to third memory dies 10 to 30 is selected, and the data stored in the selected memory die is outputted. Then, another memory die is selected, and the data stored in the selected memory die is outputted.

"For example, high-level data are stored in the first to third memory dies 10 to 30. Then, the first memory die 10 among the first to third memory dies 10 to 30 is selected, and the data stored in the first memory die 10 are outputted through the first to third data input/output TSV DQ_TSV1, DQ_TSV2, and DQ_TSV3. Then, whether all of the data outputted from the first memory die 10 are at a high level or not is checked. After the test for the first memory die 10 is ended, the second memory die 20 is selected. The data stored in the second memory die 20 are outputted through the first to third data input/output TSV DQ_TSV1, DQ_TSV2, and DQ_TSV3. Then, whether all of the data outputted from the second memory die 20 are at a high level or not is checked. After the test for the second memory die 20 is ended, the third memory die 30 is selected. The data stored in the third memory die 30 are outputted through the first to third data input/output TSV DQ_TSV1, DQ_TSV2, and DQ_TSV3. Then, whether all of the data outputted from the third memory die 30 are at a high level or not is checked.

"In the conventional semiconductor apparatus, the respective memory dies stacked therein are tested as the above. Therefore, the number of tests to be performed is decided according to the number of memory dies stacked in the semiconductor apparatus. Accordingly, when the test number of the semiconductor apparatus increases, the productivity of the semiconductor apparatus decreases."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "In one embodiment of the present invention, a semiconductor apparatus includes a test unit including: a data determination unit configured to receive a plurality of data, determine whether the plurality of data are identical or not, and output the determination result as a compression signal; and an output control unit configured to output the compression signal as a test result in response to a test mode signal and a die activation signal.

"In an embodiment of the present invention, a semiconductor apparatus includes: a first memory die configured to be enabled in response to a first memory die activation code; a second memory die configured to be enabled in response to a second memory die activation code; a first TSV configured to couple the first and second memory dies; and a second TSV configured to couple the first and second memory dies, wherein the first memory die includes first and second test units, activates one of the first and second test units in response to the first memory die activation code, and outputs a test result of the first memory die through the second TSV, and the second memory die includes third and fourth test units, activates one of the third and fourth test units in response to the second memory die activation code, and outputs a test result of the second memory die through the second TSV.

"In an embodiment of the present invention, a test method of a semiconductor apparatus includes the steps of: storing the same data in first and second memory dies during a test; inputting a first memory die activation code to the first memory die and inputting a second memory die activation code to the second memory die so as to activate both of the first and second memory dies; activating one of a plurality of test units included in the first memory die in response to the first memory die activation code; activating one of a plurality of test units included in the second memory die in response to the second memory die activation code; determining whether all of data outputted from the first memory die are identical or not, through an activated test unit included in the first memory die, and outputting the determination result through a first data input/output TSV; and determining whether all of data outputted from the second memory die are identical or not, through an activated test unit included in the second memory die, and outputting the determination result through a second data input/output TSV.

"In an embodiment of the present invention A multi chips system, comprises a plurality of chips configured to be stacked; a plurality of TSV configured to form to penetrate the plurality of chips; and a plurality of test units configured to form in every chip, and couple the plurality of TSV, respectively, wherein one of the plurality of test units which is formed in the same chip is configured to select in every chip, to generate a test result, and the test result is outputted through a selected TSV coupled to the selected test unit.

BRIEF DESCRIPTION OF THE DRAWINGS

"Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

"FIG. 1 is a cross section view of a conventional semiconductor apparatus;

"FIG. 2 is a circuit diagram of a test unit according to one embodiment of the present invention; and

"FIG. 3 is a block diagram of a semiconductor apparatus including the test unit according to the embodiment of the present invention."

For additional information on this patent application, see: KIM, Dae Suk. Semiconductor Apparatus, Test Method Using the Same and Muti Chips System. Filed March 18, 2013 and posted July 3, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4672&p=94&f=G&l=50&d=PG01&S1=20140626.PD.&OS=PD/20140626&RS=PD/20140626

Keywords for this news article include: Electronics, Sk Hynix Inc, Semiconductor.

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Source: Electronics Newsweekly


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