News Column

Researchers Submit Patent Application, "Method for Forming Copper Wiring", for Approval

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors ISHIZAKA, Tadahiro (Yamanashi, JP); HASEGAWA, Toshio (Yamanashi, JP), filed on December 20, 2013, was made available online on July 3, 2014.

The patent's assignee is Tokyo Electron Limited.

News editors obtained the following quote from the background information supplied by the inventors: "Various processes such as film formation, etching and the like are repeatedly performed on a semiconductor wafer to manufacture a desired semiconductor device. Recently, in order to meet demands for high-speed semiconductor device, miniaturization of a wiring pattern and high level of integration, it is required to realize low resistance of wiring (high conductivity) and high electromigration resistance.

"Accordingly, copper (Cu) having a high electromigration resistance and a higher conductivity (lower resistance) has been investigated as an alternative wiring material to Al or W.

"As for the Cu wiring forming method, there has been proposed a technique including: forming a barrier film formed of Ta, Ti, TaN, TiN or the like on an entire interlayer insulating film having a trench or a hole by a plasma sputtering as an example of a physical vapor deposition (PVD); forming a Cu seed film on the barrier film by the plasma sputtering; filling a trench or a hole by performing a Cu plating; and removing a residual Cu thin film or a residual barrier film remaining on the wafer surface by a chemical mechanical polishing (CMP) (see, e.g., Japanese Patent Application Publication No. 2006-148075). A PVD-TaN film attracts attention as a barrier film due to its high barrier properties.

"However, along with the progress of the miniaturization of a design rule of a semiconductor device, a hole diameter or a width of a trench has reached several tens of nm, and the formation of a Cu wiring in a recess such as a small trench or a small hole leads to an increase of a wiring resistance. The low resistance of the Cu wiring can be realized by minimizing the thickness of the barrier film to increase the volume of Cu in the recess. However, when the barrier film is formed by PVD as in a conventional case, it is difficult to form a thin and conformal barrier film in the recess."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In view of the above, the present invention provides a Cu wiring forming method capable of forming a thin and conformal barrier film in a recess and realizing a low resistance of a Cu wiring while ensuring high barrier properties.

"The present inventors have repeatedly studied in order to solve the above problems. As a result, they have found that a thin and conformal barrier film can be realized by forming a TaAlN film in a recess by thermal ALD or thermal CVD. Further, it has been found that if the film contains Al, the film can be amorphized even by ALD and the high barrier properties can be obtained. Accordingly, even if the barrier film is thin, the barrier property can be maintained and the low resistance of the wiring can be realized by decreasing the volume of the barrier film and increasing the volume of Cu in the wiring.

"In accordance with an aspect of present invention, there is provided a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess, which is formed in a substrate in a predetermined pattern, the Cu wiring forming method including: forming a barrier film of a TaAlN film at least on a surface of the recess by thermal ALD or thermal CVD; forming a Cu film to fill the recess with the Cu film; and forming a Cu wiring in the recess by polishing the entire surface of the substrate by CMP.

"A Ru film may be formed by CVD after the barrier film is formed and before the Cu film is formed.

"After or during the formation of the TaAlN film, the TaAlN film is preferably subjected to plasma processing to be modified by ion impact applied thereto. The plasma is preferably generated by applying a high frequency power to a mounting table on which the substrate is mounted. The plasma may be an Ar plasma.

"When the TaAlN film as the barrier film is formed by thermal ALD, the forming the barrier film includes: a TaN unit film forming step of repeating a predetermined number of times a cycle of supplying a Ta compound as a Ta source material into a processing chamber and adsorbing the Ta compound onto the substrate, purging the processing chamber, converting the adsorbed Ta compound to TaN by nitriding/reduction, and purging the processing chamber: and an AlN unit film forming step of repeating a predetermined number of times a cycle of supplying an Al compound as an Al source material into a processing chamber and adsorbing the Al compound onto the substrate, purging the processing chamber, converting the adsorbed Al compound to AlN by nitriding/reduction, and purging the processing chamber, wherein the ratio between the cycle in the TaN unit film forming step and the cycle in the AlN unit film forming step is set such that an atomic number ratio of Ta:Al in the film satisfies a predetermined value, and the TaN unit film forming step and the AlN unit film forming step are repeated for a specified number of times. The cycle in the TaN unit film forming step is performed 4 to 8 times, and the cycle in the AlN unit film forming step is performed once. The Al source may be adsorbed onto the substrate in an initial stage of film formation. The TaAlN film as the barrier film preferably has a thickness of 2 nm or less.

"The formation of the Cu film is performed by an apparatus for producing a plasma from a plasma generating gas in a processing chamber where the substrate is accommodated, scattering particles from a Cu target, ionizing particles in the plasma, and attracting ions onto the substrate by applying a bias power to the substrate.

"In accordance with another aspect of the present invention, there is provided a storage medium storing a program executed on a computer to control a Cu wiring forming system, wherein the program, when executed on the computer, controls the Cu wiring forming system to perform the Cu wiring forming method.

"In accordance with such configurations, a thin and conformal barrier film can be formed in a recess by using a TaAlN film formed by thermal ALD or thermal CVD. Accordingly, the film is amorphized to have high barrier property. The thin barrier film enables the volume of Cu in the wiring to be increased, so that the low resistance of the Cu wiring can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

"The objects and features of the present invention will become apparent from the following description of embodiments, given in conjunction with the accompanying drawings, in which:

"FIG. 1 is a flow chart showing a Cu wiring forming method in accordance with an embodiment of the present invention;

"FIGS. 2A to 2F are process cross sectional views for explaining the Cu wiring forming method in accordance with the embodiment of the present invention;

"FIG. 3 is a flow chart showing an example of a sequence of forming a TaAlN film as a barrier film;

"FIG. 4 is a flow chart showing another example of a sequence of forming a TaAlN film as a barrier film;

"FIG. 5 is a flow chart showing still another example of a sequence of forming a TaAlN film as a barrier film;

"FIG. 6 is a flow chart showing still another example of a sequence of forming a TaAlN film as a barrier film;

"FIG. 7 shows a result of a test that has examined barrier properties depending on conditions of formation of a TaAlN film as a barrier film;

"FIG. 8 is a top view showing an example of a multi-chamber type film forming system suitable for implementation of a Cu wiring forming method in accordance with an embodiment of the present invention;

"FIG. 9 is a cross sectional view showing a Cu film forming apparatus for forming a Cu film, which is installed in the film forming system shown in FIG. 8;

"FIG. 10 is a cross sectional view showing a barrier film forming apparatus for forming a barrier film formed of a TaAlN film, which is installed in the film forming system shown in FIG. 8; and

"FIG. 11 is a cross sectional view showing a Ru liner film forming apparatus for forming a Ru liner film, which is installed in the film forming system shown in FIG. 8."

For additional information on this patent application, see: ISHIZAKA, Tadahiro; HASEGAWA, Toshio. Method for Forming Copper Wiring. Filed December 20, 2013 and posted July 3, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6991&p=140&f=G&l=50&d=PG01&S1=20140626.PD.&OS=PD/20140626&RS=PD/20140626

Keywords for this news article include: Electronics, Semiconductor, Tokyo Electron Limited.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters