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Researchers Submit Patent Application, "Memory System", for Approval

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors MOON, Young Suk (Icheon-si, KR); Lee, Hyung Dong (Icheon-si, KR); Kwon, Yong Kee (Icheon-si, KR); Yang, Hyung Gyun (Icheon-si, KR), filed on March 18, 2013, was made available online on July 3, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Various embodiments generally relate to a semiconductor apparatus, and more particularly, to a memory system including a plurality of chips or dies stacked therein.

"In order to increase the integration degree of a semiconductor apparatus, a three-dimensional (3D) semiconductor apparatus in which a plurality of chips are stacked and packaged has been developed. The 3D semiconductor apparatus may include two or more chips stacked in a vertical direction, thereby realizing the maximum integration degree in the same space.

"Furthermore, in order to improve operation performance, a memory system including a memory controller or processor has been developed. The memory system includes a memory core to store data, wherein the memory core communicates with a host through the memory controller or processor.

"Meanwhile, since a memory apparatus such as a dynamic random-access memory (DRAM) has a characteristic of a volatile storage device, the memory apparatus performs a refresh operation to preserve data stored in a memory cell at each predetermined period (that is, retention time). The memory apparatus is vulnerable to deterioration. Therefore, as the temperature of the memory apparatus increases, the refresh operation must be performed at a shorter period. Accordingly, many techniques for changing the refresh period depending on the temperature of the memory apparatus have been proposed.

"FIG. 1 schematically illustrates a conventional memory system when a processor is in a sleeping mode. Referring to FIG. 1, a plurality of stacked memory dies MEMORY1 to MEMORY4 and the processor construct a memory system. The processor communicates with a host (not illustrated), and relays communication between the stacked memory dies MEMORY1 to MEMORY4 and the host.

"When the processor is in the sleeping mode, the temperature of the processor is not increased much. Therefore, the temperatures of the stacked memory dies MEMORY1 to MEMORY4 are not changed much. For example, as illustrated in FIG. 1, the first memory die MEMORY1 may be heated to 36.degree. C., the second memory die MEMORY2 may be heated to 34.degree. C., the third memory die MEMORY3 may be heated to 32.degree. C., and the fourth memory die MEMORY4 may be heated to 30.degree. C. In this case, a retention time corresponding to a period at which a refresh operation must be performed may be set in the range of 74 ms to 80 ms. Therefore, a small amount of current is consumed during the refresh operation.

"FIG. 2 schematically illustrates the conventional memory system when the processor operates. Referring to FIG. 2, when the processor operates, the temperatures of the memory dies MEMORY1 to MEMORY4 may be rapidly increased. For example, as illustrated in FIG. 2, the third memory die MEMORY3 may be heated to 110.degree. C., the fourth memory die MEMORY4 may be heated to 90.degree. C., and the first and second memory dies MEMORY1 and MEMORY2 may be heated to 120.degree. C. and 110.degree. C., respectively.

"As the temperatures of the first and second memory dies MEMORY1 and MEMORY2 are increased to 120.degree. C. and 110.degree. C., respectively, the first and second memory dies MEMORY1 and MEMORY2 require a very short data retention time of 10 ms to 25 ms. Accordingly, since the memory dies must perform a refresh operation at a short period, the amount of current consumed during a refresh operation is rapidly increased. Furthermore, as a data storage region to be refreshed is increased, the bandwidth of a channel to input and output data is significantly decreased."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "A memory system which transfers data stored in a volatile memory die to a nonvolatile memory die as a backup such that the volatile memory die does not need to perform a refresh operation is described herein.

"In an embodiment of the present invention, a memory system includes: a processor; one or more volatile memory dies stacked with the processor; and one or more nonvolatile memory dies stacked with the processor and the volatile memory dies, wherein the processor transfers data stored in the volatile memory die to the nonvolatile memory die in response to a backup signal, and transfers the data stored in the nonvolatile memory die to the volatile memory die in response to a recovery signal.

"In an embodiment of the present invention, a memory system includes: a processor configured to communicate with a host; a logic die configured to communicate with the processor; one or more volatile memory dies stacked with the logic die; and one or more nonvolatile memory dies stacked with the logic die and the volatile memory dies, wherein the logic die transfers data stored in the volatile memory die to the nonvolatile memory die in response to a backup signal, and transfers the data stored in the nonvolatile memory die to the volatile memory die in response to a recovery signal.

"In an embodiment of the present invention, a memory system includes: a processor; and one or more volatile memory dies stacked with a nonvolatile memory die and the processor, wherein the processor performs a data transfer operation when a backup signal and/or a recovery signal is generated.

BRIEF DESCRIPTION OF THE DRAWINGS

"Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

"FIG. 1 schematically illustrates a conventional memory system and temperatures and retention times of memories when a processor is in a sleeping mode;

"FIG. 2 schematically illustrates the conventional memory system and temperatures and retention times of memories when the processor operates;

"FIG. 3 is a block diagram illustrating the configuration of a memory system according to one embodiment of the present invention;

"FIG. 4 is diagram to conceptually explain the operation of an address mapping unit of FIG. 3;

"FIG. 5 is a diagram illustrating the operation of the address mapping unit when data are transferred from nonvolatile memory dies to a nonvolatile memory die;

"FIG. 6 is a diagram illustrating the operation of the address mapping unit when data are recovered from the nonvolatile memory die into the volatile memory dies; and

"FIG. 7 is a diagram illustrating the configuration of a memory system according to another embodiment of the present invention."

For additional information on this patent application, see: MOON, Young Suk; Lee, Hyung Dong; Kwon, Yong Kee; Yang, Hyung Gyun. Memory System. Filed March 18, 2013 and posted July 3, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=599&p=12&f=G&l=50&d=PG01&S1=20140626.PD.&OS=PD/20140626&RS=PD/20140626

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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