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Researchers Submit Patent Application, "Gate Structure Formation Processes", for Approval

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors CHOI, Dae-Han (Loudonville, NY); HWANG, Wontae (Clifton Park, NY); KHANNA, Puneet (Clifton Park, NY), filed on December 20, 2012, was made available online on July 3, 2014.

The patent's assignee is Globalfoundries, Inc.

News editors obtained the following quote from the background information supplied by the inventors: "The gate structure (or gate or transistor gate) is the transistor terminal that modulates channel conductivity. Two principle approaches for forming semiconductor device gate structures are the gate-first and gate-last process approaches.

"During fabrication of gate structures for, for instance, complementary metal-oxide-semiconductor (CMOS) technology, gate-first fabrication has traditionally been employed. In a gate-first fabrication approach, a conductor is provided over a gate dielectric, and then patterned (i.e., etched) to form one or more gate structures. After forming the gate structures, source and drain features of the semiconductor devices are provided.

"More recently, the gate-last approach (or replacement metal gate (RMG) approach), has been employed. In the gate-last approach, a sacrificial (or dummy) gate material is provided and patterned (i.e., etched) to define one or more sacrificial gates. The one or more sacrificial gates are subsequently replaced with, for instance, a metal gate, after source and drain features of the devices have been formed. The sacrificial gate material holds the position for the subsequent metal gate to be formed. For instance, an amorphous silicon (a-Si) or polysilicon sacrificial gate may be patterned and used during initial processing until high-temperature annealing to activate the source and drain features has been completed. Subsequently, the a-Si or polysilicon may be removed and replaced with the final metal gate.

"As noted, in both the gate-first and gate-last approaches, a complicated gate material etch process is required. This process is problematic as critical dimensions continually become smaller."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method which includes, for instance: providing a sacrificial layer over a substrate; patterning the sacrificial layer to form a gate opening within the sacrificial layer; providing a gate structure within the gate opening in the sacrificial layer; and removing the sacrificial layer, leaving the gate structure over the substrate.

"In another aspect, a method is provided which includes: providing a sacrificial layer over a substrate; patterning the sacrificial layer to form a plurality of gate openings within the sacrificial layer; providing a plurality of gate structures within the plurality of gate openings in the sacrificial layer; and removing the sacrificial layer, leaving the plurality of gate structures over the substrate.

"In a further aspect, a semiconductor device is presented which includes a substrate and a plurality of gate structures disposed over the substrate. At least one gate structure of the plurality of gate structures includes a reverse sidewall-spacer and a gate material, wherein the reverse sidewall spacer curves inwardly in a upper region thereof towards the gate material.

"Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

"One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

"FIG. 1 depicts one embodiment of a process for fabricating a transistor using a gate-first approach;

"FIG. 2 depicts one embodiment of a process for fabricating a transistor using a gate-last approach;

"FIG. 3 depicts one embodiment of a process for fabricating, for instance, a transistor using a novel gate structure fabrication approach, in accordance with one or more aspects of the present invention;

"FIG. 4A depicts one embodiment of a structure obtained during a gate structure fabrication approach, in accordance with one or more aspects of the present invention;

"FIG. 4B depicts the structure of FIG. 4A after patterning one or more gate openings within the sacrificial layer, in accordance with one or more aspects of the present invention;

"FIG. 4C depicts the structure of FIG. 4B after provision of reverse sidewall-spacers in the gate openings within the sacrificial layer, in accordance with one or more aspects of the present invention;

"FIG. 4D depicts the structure of FIG. 4C after provision of one or more layers of gate structure materials over the sacrificial layer, including within the plurality of gate openings, in accordance with one or more aspects of the present invention;

"FIG. 4E depicts the structure of FIG. 4D after planarizing the one or more layers of gate materials down to the sacrificial layer, to define one or more gate structures within the one or more gate openings, in accordance with one or more aspects of the present invention;

"FIG. 4F depicts the structure of FIG. 4E after partial recessing of the one or more gate structures, in accordance with one or more aspects of the present invention;

"FIG. 4G depicts the structure of FIG. 4F after provision of a gate cap layer over the sacrificial layer, including within the gate recess(es) in the gate structure(s), in accordance with one or more aspects of the present invention; and

"FIG. 4H depicts one embodiment of the resultant gate structures obtained after planarizing the gate cap layer down to the sacrificial layer, and then removing the sacrificial layer, leaving the gate structure(s) over the substrate, in accordance with one or more aspects of the present invention."

For additional information on this patent application, see: CHOI, Dae-Han; HWANG, Wontae; KHANNA, Puneet. Gate Structure Formation Processes. Filed December 20, 2012 and posted July 3, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2945&p=59&f=G&l=50&d=PG01&S1=20140626.PD.&OS=PD/20140626&RS=PD/20140626

Keywords for this news article include: Electronics, Semiconductor, Globalfoundries Inc..

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Source: Electronics Newsweekly


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