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Researchers Submit Patent Application, "Channel Control Circuit and Semiconductor Device Having the Same", for Approval

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor KIM, Ki Tae (Icheon-si, KR), filed on March 18, 2013, was made available online on July 3, 2014.

The patent's assignee is Sk Hynix Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Various embodiments generally relate to a semiconductor device, and more particularly to a semiconductor device having high test efficiency.

"The demand for high-speed, multi-functional and miniaturized semiconductor device continues to grow. A chip scale package is a part of the efforts to develop such a semiconductor device. For example, a System on Chip (SoC) is an integrated circuit that integrates various components of an electronic system into a single chip. In the System on Chip, a plurality of bump pads can be disposed.

"FIG. 1 is a schematic block diagram illustrating a known SoC having a wide-IO DRAM.

"Referring to FIG. 1, an SoC 1 includes four channels ch A, ch B, ch C, and ch D.

"Each of the channels includes four banks BK0, BK1, BK2, and BK3.

"Each channel includes a peripheral region PERI thereof, and the peripheral regions PERIs include the respective clock buffers 10a, 10b, 10c, and 10d therein. The channels ch A, ch B, ch C, and ch D include the respective bump pad groups a, b, c, and d to transmit and receive signals to and from an external system. The respective bump pad groups a, b, c, and d, include bump pads provided for clock, address, command, DQ, and power.

"In addition, a semiconductor device may have pads PAD for probe test on the center column thereof.

"In order for a system provider to estimate the characteristics of a DRAM itself, a mode of applying an input directly to the DRAM, without passing through a system, is required. In order to test memory cells in the banks of each channel, a direct access (hereinafter, referred to as 'DA') mode test method is used. In the DA mode, since a function test needs to be performed with a minimum number of bump pads, input signals are transmitted to and received from all channels in common.

"FIG. 1 illustrates a case where the respective clock buffers 10a, 10b, 10c, and 10d are coupled to one bump pad for clock in common, in a DA mode. A signal applied to one bump pad is applied to the respective corresponding channel signal units in common.

"However, it is impossible in a DA mode to perform a boundary test, which is performed to check defects in bump pads, on each channel individually. In addition, since signals of all channels are applied in common, it is impossible to control electrical fuses of each channel individually. Moreover, it is impossible in a DA mode to measure the amount of current by channel, which is required in the Wide IO JEDEC Standard."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "A semiconductor device having improved test efficiency by enabling a test freely from a structural connection for providing a DA mode in the DA mode is described herein.

"In an embodiment of the present invention, a channel control circuit of a semiconductor device includes: a channel control is signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal, a first scan signal, and a second scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal which controls whether to activate a clock input buffer in response to the channel control signal and the scan buffer control signal; and the clock input buffer configured to generate a clock output signal in response to a clock signal and the clock buffer control signal.

"In an embodiment of the present invention, a channel control circuit of a semiconductor device is included in each of a plurality of channels, and is configured to be able to control only one predetermined channel to be selected and activated and the remaining channels to be at an inactivated state, in a DA mode for simultaneously testing the plurality of channels of the semiconductor device which includes the plurality of channels.

"According to an embodiment of the present invention, while a structural connection is formed to receive the same signal in order to operate in a DA mode, it is possible to transition from the synchronous channel mode to a mode of independently operating one channel properly using test mode signals. Accordingly, various tests can be performed according to each channel, thereby being able to is improve test efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

"Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

"FIG. 1 is a schematic block diagram of a channel control circuit of a known semiconductor device;

"FIG. 2 is a block diagram of a semiconductor device according to an embodiment of the present invention;

"FIG. 3 is a circuit diagram of a channel control signal generating block capable of being implemented in the block diagram of FIG. 2;

"FIG. 4 is a block diagram of a scan buffer control signal generating block capable of being implemented in the block diagram of FIG. 2;

"FIG. 5 is a circuit diagram of a clock buffer control signal generating block capable of being implemented in the block diagram of FIG. 2; and

"FIG. 6 is a timing diagram illustrating the operation of a channel control circuit capable of being implemented in the block diagram of FIG. 2."

For additional information on this patent application, see: KIM, Ki Tae. Channel Control Circuit and Semiconductor Device Having the Same. Filed March 18, 2013 and posted July 3, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=434&p=9&f=G&l=50&d=PG01&S1=20140626.PD.&OS=PD/20140626&RS=PD/20140626

Keywords for this news article include: Electronics, Sk Hynix Inc, Semiconductor.

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Source: Electronics Newsweekly


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