The patent's assignee for patent number 8766101 is
News editors obtained the following quote from the background information supplied by the inventors: "Conventionally, various types of wiring substrates are proposed for mounting a semiconductor chip thereon.
"For example, there is proposed a wiring substrate that includes a first wiring part having plural wiring layers, a second wiring part mounted on the first wiring part and having a thermal expansion rate smaller than that of the first wiring part, and a semiconductor chip mounted on the second wiring part and having a thermal expansion rate substantially equal to that of the second wiring part. Further, there is proposed a wiring substrate that includes a wiring pattern formed on a silicon substrate. Patent Document 1: Japanese Laid-Open Patent Publication No. 2006-270037 Patent Document 2: International Publication Pamphlet No. WO 05/114728
"A wiring substrate for mounting a semiconductor chip thereon is desired to have a connection reliability that can endure stress caused by the difference of thermal expansion rates. It is also desired for the wiring substrate to be capable of forming narrow pitch external connection terminals (e.g., solder bumps) in correspondence with electrode terminals of the semiconductor chip."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "According to an aspect of the invention, there is provided a wiring substrate including: an inorganic substrate including a substrate body formed of an inorganic material, a wiring pattern formed on the substrate body, and an external connection terminal being electrically connected to the wiring pattern; an organic substrate that is formed below the inorganic substrate, the organic substrate including an insulating layer and a wiring layer formed on the insulating layer; and a bonding layer interposed between the inorganic substrate and the organic substrate, the bonding layer including a stress buffer layer and a penetration wiring that penetrates the stress buffer layer. A thermal expansion coefficient of the stress buffer layer is greater than a thermal expansion coefficient of the inorganic substrate and less than a thermal expansion coefficient of the organic substrate. The wiring pattern and the wiring layer are electrically connected by way of the penetration wiring.
"The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
"It is to be understood that both the foregoing generation description and the followed detailed description are exemplary and explanatory and are not restrictive of the invention as claimed."
For additional information on this patent, see:
Keywords for this news article include: Electronics, Semiconductor,
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